TUSB8020BPHPR datasheet(25/43 Pages) TI1

25 / 43 page

TUSB8020B

www.ti.com

SLLSEF6A – JULY 2014 – REVISED JULY 2014

8.5.1.23 Device Status and Command Register (offset = F8h)

Figure 25. Register Offset F8h

RSU

RCU

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Table 24. Bit Descriptions – Device Status and Command Register

Bit

Field Name

Access

Reset

Description

7:2

RSVD

Reserved. Read only, returns 0 when read.

SMBus interface reset. This bit loads the registers back to their GRSTz values.

smbusRst

RSU

This bit is set by writing a 1 and is cleared by hardware on completion of the reset. A

write of 0 has no effect.

Configuration active. This bit indicates that configuration of the TUSB8020B is currently

active. The bit is set by hardware when the device enters the I2C or SMBus mode. The

TUSB8020B will not connect on the upstream port while this bit is 1.

cfgActive

RCU

When in the SMBus mode, this bit must be cleared by the SMBus host to exit the

configuration mode and allow the upstream port to connect.

The bit is cleared by a writing 1. A write of 0 has no effect.

Submit Documentation Feedback

Product Folder Links: TUSB8020B

TUSB8020BPHPR Datasheet(PDF) 25 Page - Texas Instruments