COM20022ITQFP datasheet(47/83 Pages) SMSC

47 / 83 page

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

Datasheet

SMSC COM20022I

Page 47

Rev. 08-18-03

DATASHEET

Table 6.13 - DMA Count Register

BIT

BIT NAME

SYMBOL

DESCRIPTION

7-0

Terminal Count

Timer Mode

Cycle Mode

TC7-TC0

TIM7-TIM0

CYC7-CYC0

TC7-TC0: Used for non-burst or burst mode. These are the lower 8

bits of the Terminal Count setting register. The MSB (TC8) is in the

Bus Control Register. The Terminal Count setting range is from 1 to

512 counts (TC8 - TC0 all zeroes means 512 counts).

TIM7-TIM0: Used for Programmable-Burst by Timer mode. These bits

are for setting the term of the continuous DMA transfer. The time

range is from 100nS to 25.6

µS. The step is 100nS (TIM7-TIM0 all

zeroes means 25.6

µs).

CYC7-CYC0: Used for Programmable-Burst by Cycle mode. These

bits are for setting the term of the continuous DMA transfer. The cycle

range is from 2 to 256 cycles. CYC7-CYC0 all zeroes means 256

cycles. (1 is illegal)

Address Pointer Register

Low

2K x 8

RAM

Data Register

I/OAddress 04H

I/OAddress 03H

11-Bit Counter

Memory

Address Bus

Memory

Data Bus

D0-D7

High

I/OAddress 02H

INTERNAL

Figure 6.2

- Sequential Access Operation

COM20022ITQFP Datasheet(PDF) 47 Page - SMSC Corporation

COM20022ITQFP Datasheet(HTML) 47 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

Datasheet Download

Link URL