MTCH6102T-ISLASHSS datasheet(9/45 Pages) MICROCHIP

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 2014 Microchip Technology Inc.

DS40001750A-page 9

MTCH6102

5.1.3

DEVICE ADDRESSING

The MTCH6102 default 7-bit base address is 0x25.

Every transmission must be prefixed with this address,

as well as a bit signifying whether the transmission is a

master write (‘0’) or master read (‘1’). After appending

this Read/Write bit to the base address, this first byte

becomes either 0x4A (write) or 0x4B (read).

This address can be modified (see I2CADDR), but this

requires initially communicating with the device under

the default address. If this is not feasible in the user’s

application, contact Microchip support for additional

options.

5.2

Interrupt Pin

MTCH6102 provides an open-collector active-low

Interrupt pin (INT) that will be asserted any time new

data is available. INT is automatically released under

two conditions:

A read is performed of any register within the

device.

The next frame of decoding has started.

5.3

SYNC Output Pin

MTCH6102 provides an active-high sync signal that

correlates with the current touch frame status. The

SYNC pin is low while the device is sleeping (between

frames) and high while touch sensing/decoding is

occurring. A common use of this pin includes a host

that makes use of data on every frame (such as

raw-acquisition data), for host-side decoding (see

Figure 5-4).

FIGURE 5-4:

EXAMPLE INT/SYNC LOGIC

INT

SYNC

Controller sleeping

INT is released as controller goes to Sleep

Controller decoding

INT is asserted due to (d)

Touch frame

INT is released due to I2C™ read

Finger is present

INT is released due to I2C™ read

INT asserted due to (d)

Finger is not present

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