SC16C654 datasheet(13/52 Pages) PHILIPS

13 / 52 page

Philips Semiconductors

SC16C654/654D

Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder

Product data

Rev. 04 — 19 June 2003

13 of 52

9397 750 11617

6.4 Internal registers

The SC16C654/654D provides 15 internal registers for monitoring and control. These

registers are shown in Table 5. Twelve registers are similar to those already available

in the standard 16C554. These registers function as data holding registers

(THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register

(FCR), line status and control registers (LCR/LSR), modem status and control

registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM),

and a user accessible scratchpad register (SPR). Beyond the general 16C554

features and capabilities, the SC16C654/654D offers an enhanced feature register

set (EFR, Xon/Xoff1-2) that provides on-board hardware/software ﬂow control.

[1]

These registers are accessible only when LCR[7] is a logic 0.

[2]

These registers are accessible only when LCR[7] is a logic 1.

[3]

Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to

“BF” (HEX).

6.5 FIFO operation

The 64-byte transmit and receive data FIFOs are enabled by the FIFO Control

level, but not the transmit trigger level. The SC16C654/654D provides independent

trigger levels for both receiver and transmitter. To remain compatible with SC16C554,

the transmit interrupt trigger level is set to 8 following a reset. It should be noted that

the user can set the transmit trigger levels by writing to the FCR register, but

activation will not take place until EFR[4] is set to a logic 1. The receiver FIFO section

includes a time-out function to ensure data is delivered to the external CPU. An

Table 5:

Internal registers decoding

READ mode

WRITE mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)[1]

Receive Holding Register

Transmit Holding Register

Interrupt Enable Register

Interrupt Status Register

FIFO Control Register

Line Control Register

Modem Control Register

Line Status Register

n/a

Modem Status Register

n/a

Scratchpad Register

Baud rate register set (DLL/DLM)[2]

LSB of Divisor Latch

MSB of Divisor Latch

Enhanced register set (EFR, Xon/off 1-2)[3]

Enhanced Feature Register

Xon1 word

Xon2 word

Xoff1 word

Xoff2 word

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