SC16C654 datasheet(21/52 Pages) PHILIPS

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Philips Semiconductors

SC16C654/654D

Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder

Product data

Rev. 04 — 19 June 2003

21 of 52

9397 750 11617

7.1 Transmit (THR) and Receive (RHR) Holding Registers

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and

Transmit Shift Register (TSR). The status of the THR is provided in the Line Status

the THR, providing that the THR or TSR is empty. The THR empty ﬂag in the LSR

transferred to the TSR. Note that a write operation can be performed when the THR

empty ﬂag is set (logic 0 = FIFO full; logic 1 = at least one FIFO location available).

The serial receive section also contains an 8-bit Receive Holding Register (RHR).

Receive data is removed from the SC16C654/654D and receive FIFO by reading the

RHR register. The receive section provides a mechanism to prevent false starts. On

the falling edge of a start or false start bit, an internal receiver counter starts counting

clocks at the 16

× clock rate. After 7-1⁄2 clocks, the start bit time should be shifted to

the center of the start bit. At this time the start bit is sampled, and if it is still a logic 0

it is validated. Evaluating the start bit in this manner prevents the receiver from

assembling a false character. Receiver status codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready,

transmitter empty, line status and modem status registers. These interrupts would

normally be seen on the INTA-INTD output pins in the 16 mode, or on wire-OR IRQ

output pin in the 68 mode.

Table 9:

Interrupt Enable Register bits description

Bit

Symbol

Description

IER[7]

CTS interrupt.

Logic 0 = Disable the CTS interrupt (normal default condition).

Logic 1 = Enable the CTS interrupt. The SC16C654/654D issues an

interrupt when the CTS pin transitions from a logic 0 to a logic 1.

IER[6]

RTS interrupt.

Logic 0 = Disable the RTS interrupt (normal default condition).

Logic 1 = Enable the RTS interrupt. The SC16C654/654D issues an

interrupt when the RTS pin transitions from a logic 0 to a logic 1.

IER[5]

Xoff interrupt.

Logic 0 = Disable the software ﬂow control, receive Xoff interrupt

(normal default condition).

Logic 1 = Enable the software ﬂow control, receive Xoff interrupt. See

Section 6.7 “Software ﬂow control” for details.

IER[4]

Sleep mode.

Logic 0 = Disable sleep mode (normal default condition).

Logic 1 = Enable sleep mode. See Section 6.13 “Sleep mode” for details.

IER[3]

Modem Status Interrupt.

Logic 0 = Disable the modem status register interrupt (normal default

condition).

Logic 1 = Enable the modem status register interrupt.

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