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MT9072AB Datasheet(PDF) 228 Page - Zarlink Semiconductor Inc |
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MT9072AB Datasheet(HTML) 228 Page - Zarlink Semiconductor Inc |
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228 / 275 page  MT9072 Data Sheet 228 Zarlink Semiconductor Inc. Figure 14 - 8 T1 Links with no JA or PLL in LIU, Slave or Master Mode, Jitter-Free ST-BUS RPOS RNEG EXCLi TPOS TNEG TXCL DSTo CSTo DSTi CSTi CKi FPi Framer 1/8 RPOS RNEG RCLK TPOS TNEG TCLK LIU 1/8 RT RR TT TR Transmit xfmr LINE 1 Receive xfmr From RCLK’s of LIU’s Notes: Framer 1-8, 1 of MT9072 LIU 1-8, 8 of Generic LIU PLL, 1 of MT9042 LDX, 1 of MT90820 - Framer elastic buffer is used. - LIU Transmit JA and PLL are bypassed. RPOS RNEG RCLK TPOS TNEG TCLK LIU 8/8 RT RR TT TR Transmit xfmr LINE 8 Receive xfmr LINES 2 to 7 Framers 2 to 7 DSTo CSTo DSTi CSTi CKi FPi LIU’s 2 to 7 STi0 STo0 STi1-6 STo1-6 STi7 STo7 STi8-15 STo8-15 F0i C4i LDX 7 7 PRI SEC F0o C2o C4o PLL RPOS RNEG EXCLi TPOS TNEG TXCL DSTo CSTo DSTi CSTi CKi FPi Framer 8/8 RXDLC |
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