MCP3919 datasheet(21/88 Pages) MICROCHIP

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 2014 Microchip Technology Inc.

DS20005347A-page 21

MCP3919

3.7

Data Ready Output/GAIN1 Logic

Input (DR/GAIN1)

The data ready pin indicates if a new conversion result

is ready to be read. The default state of this pin is logic

high when DR_HIZ = 1 and is high-impedance when

DR_HIZ = 0 (default). After each conversion is

finished, a logic low pulse will take place on the data

ready pin to indicate the conversion result is ready as

an interrupt. This pulse is synchronous with the master

clock and has a defined and constant width.

The data ready pin is independent of the SPI interface

and acts like an interrupt output. The data ready pin

state is not latched, and the pulse width (and period)

are both determined by the MCLK frequency,

over-sampling rate, and internal clock prescale

settings. The data ready pulse width is equal to half a

DMCLK period and the frequency of the pulses is equal

to DRCLK (see Figure 1-3).

In the 2-Wire Interface mode, this is the GAIN1 logic

select input pin (See Section 7.0 “2-Wire Serial Inter-

face Description”

for the logic input table for GAIN0

and GAIN1). The pin state is latched when the MODE

changes to 2-Wire Interface mode and is relatched at

each watchdog timer reset.

3.8

Crystal Oscillator/Master Clock

Input/GAIN0 Logic Input Pin

(OSC1/CLKI/GAIN0)

OSC1/CLKI and OSC2 provide the master clock for the

device. When CLKEXT = 0, a resonant crystal or clock

source with a similar sinusoidal waveform must be

placed across the OSC1 and OSC2 pins to ensure

proper operation.

The typical clock frequency specified is 4 MHz. For

proper operation, and for optimizing ADC accuracy,

AMCLK should be limited to the maximum frequency

defined in Table 5-2 for the function of the BOOST and

PGA setting chosen. MCLK can take larger values as

long as the prescaler settings (PRE<1:0>) limit

AMCLK = MCLK/PRESCALE in the defined range in

Table 5-2. Appropriate load capacitance should be

connected to these pins for proper operation.

In 2-Wire Interface mode, this is the GAIN1 logic select

input pin (See Section 7.0 “2-Wire Serial Interface

Description”

for the logic input table for GAIN0 and

GAIN1). The pin state is latched when the MODE

changes to 2-Wire Interface mode, and is relatched at

each watchdog timer reset.

3.9

Crystal Oscillator Output/Interface

MODE Logic Input (OSC2/MODE)

When CLKEXT = 0, a resonant crystal or clock source

with a similar sinusoidal waveform must be placed

across the OSC1 and OSC2 pins to ensure proper

operation. Appropriate load capacitance should be

connected to these pins for proper operation.

When CLKEXT = 1 (default condition at POR), this pin

is the MODE selection pin for the digital interface.

When MODE is logic low, the SPI interface is selected

(see Section 6.0 “SPI Serial Interface Description”);

when MODE is logic high, the 2-Wire interface (see

Section 7.0 “2-Wire Serial Interface Description”

) is

selected. The MODE input is latched after a POR, a

Master Reset and/or a watchdog timer reset.

3.10

Chip Select/Boost Logic Input

(CS/BOOST)

This pin is the Serial Peripheral Interface (SPI) chip

select that enables serial communication. When this

pin is logic high, no communication can take place. A

chip select falling edge initiates serial communication,

and a chip select rising edge terminates the

communication. No communication can take place

even when CS is logic low, if RESET is also logic low.

This input is Schmitt-triggered.

In 2-Wire Interface mode, this is the BOOST logic

select input pin (see Section 7.0 “2-Wire Serial Inter-

face Description”

for the logic input table for BOOST).

The pin state is latched when the MODE changes to 2-

Wire Interface mode, and is relatched at each watch-

dog timer reset.

Note:

This pin should not be left floating when

the DR_HIZ bit is low; a 100 k

 pull-up

resistor

connected

DVDD

recommended.

Note:

When CLKEXT = 1, the crystal oscillator

is disabled. OSC1 becomes the master

clock input CLKI, a direct path for an

external clock source. One example

would be a clock source generated by an

MCU.

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