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MCP3919 Datasheet(PDF) 55 Page - Microchip Technology |
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MCP3919 Datasheet(HTML) 55 Page - Microchip Technology |
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55 / 88 page  2014 Microchip Technology Inc. DS20005347A-page 55 MCP3919 FIGURE 7-2: Frame Word. These four frames can be used to multiplex SDO at the output of the digital isolators. In this case, up to four channels (typically three phases and one neutral for energy metering applications) can be multiplexed. The output data of each individual MCP3919 device can be attributed to a different frame (FRAME0, 1, 2 or 3) and retrieved on a single SDO line after the digital isolators, provided that the isolators have a chip enable or a multiplexing feature. The frame counter can then be used to retrieve the information about which MCP3919 part is actually being read. After the four frames have been transmitted, the SDO pin idles logic low to reduce digital isolator power consumption until the next data is available. If OSR = 64, the SDO never idles because the data is directly available after the four frames are transmitted. Figure 7-3 displays the timing diagram for 2-Wire Interface mode, showing all OSR possibilities. Note that the first set of frames is sent only when the first data is ready, which means that the set- tling time of the sinc filter will be elapsed before sending the first set of frames as represented in Figure 7-3. It should also be noted that since the PHASE register is back to its default value in the 2-Wire mode, there is no delay between the two channels in this mode and the conversions start after a delay of OSR/2 DMCLK periods (which corresponds to 2 x OSR MCLK periods). FIGURE 7-3: MCP3919 2-Wire Communication Protocol. CH1 CH0 SYNC 0 1 0 1 0 1 0 1 ADCCH0 24bits ADCCH1 24bits ADCCH2 24bits SYNC1 SYNC0 FRAME CH2 CRC COM 16bits CRC CH1 CH0 SYNC 0 1 0 1 0 1 0 1 ADCCH0 16bits ADCCH1 16bits ADCCH2 16bits SYNC1 SYNC0 FRAME CH2 Frame Clocking for OSR = 64 Frame Clocking for OSR > 64 TABLE 7-4: FRAME COUNTER SETTINGS CNT1 CNT0 FRAME NUMBER 00 FRAME0 01 FRAME1 10 FRAME2 11 FRAME3 SDO (OSR=64) OSC2/MODE SCK/MCLK 2-Wire Mode (2*OSR)x clocks Hi-Z Hi-Z Hi-Z Hi-Z SDO (OSR=128) SDO (OSR=256) SDO (OSR=512) 256x clocks 256x clocks 256x clocks 256x clocks 256x clocks 256x clocks 256x clocks 256x clocks 256x clocks 256x clocks 256x clocks 256x clocks 256x clocks 256x clocks 256x clocks 256x clocks 256x clocks 256x clocks 256x clocks 256x clocks 256x clocks 256x clocks 256x clocks 0 DATA=D1 DATA=D2 DATA=D3 DATA=D4 DATA=D5 DATA=D6 DATA=D7 DATA=D8 DATA=D9 DATA=D10 DATA=D11 DATA=D12 DATA=D13 DATA=D14 DATA=D15 DATA=D16 DATA=D17 DATA=D18 DATA=D19 DATA=D20 DATA=D21 DATA=D22 DATA=D23 DATA=D24 0 0 0 00 0 0 0 Internal data ready (Data is unsettled). No frame is transmitted Data Ready. New data is available 256x clocks 256x clocks 256x clocks 256x clocks 256x clocks 256x clocks 256x clocks 256x clocks DATA=D25 DATA=D26 DATA=D27 DATA=D28 DATA=D29 0 0 -OSR/2 0 256x clocks 0 0 0 0 0 0 0 0 0 |
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