PC87373 datasheet(65/174 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

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3.14.5 GPIO Event Routing Register (GPEVR)

This register enables the routing of the GPIO event (see Section 5.3.2 on page 76) to an IRQ. An exception to this is GPIO14

pin of Port 1, which lacks the GPEVR register (the register is reserved). GPEVR is reset to 00h.

Power Well: VSB3

Location:

Index F2h

Type:

R/W or RO

R/W or

EVTYPE (Event Type). This bit deﬁnes the type of the wake-up signal that issues an event from the

selected GPIO pin (see Section 5.3 on page 75).

0: Edge input (default)

1: Level input

R/W1S LOCKCFP (Lock Configuration of Pin). When set to 1, this bit locks the GPIO pin conﬁguration and

data (see also Section 5.4 on page 77) by disabling writing to itself, to GPCFG1 register bits PUPCTL,

OUTTYPE and OUTENA, to all of the bits of GPCFG2 register and to the corresponding bit in GPDO

and GPDIO registers. Once set, this bit can be cleared by VDD3 Power-Up reset (or Hardware reset).

0: R/W bits are enabled for write (default)

1: All bits are RO

R/W or

PUPCTL (Pull-Up Control). This bit controls the internal pull-up resistor of the selected GPIO pin (see

Section 5.2 on page 74).

0: Disabled (default)

1: Enabled

R/W or

OUTTYPE (Output Type). This bit controls the output buffer type of the selected GPIO pin (see Section

5.2 on page 74).

0: Open-drain (default)

1: Push-pull

R/W or

OUTENA (Output Enable). This bit controls the output buffer of the selected GPIO pin (see Section 5.2

on page 74).

0: TRI-STATE (default)

1: Output buffer enabled

Bit

76543210

Name

Reserved

EV2IRQ

Reset

00000000

Bit

Description

7-1

Reserved.

EV2IRQ (Event to IRQ Routing). Controls the routing of the event from the selected GPIO pin to IRQ (see

Section 5.3.2 on page 76).

0: Disabled (default)

1: Enabled

Bit

Type

Description

PC87373 Datasheet(PDF) 65 Page - National Semiconductor (TI)

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