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8P34S2108NLGI Datasheet(PDF) 9 Page - Integrated Device Technology

Part # 8P34S2108NLGI
Description  Dual 1:8 LVDS Output 1.8V Fanout Buffer
PDF  20 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

8P34S2108NLGI Datasheet(HTML) 9 Page - Integrated Device Technology

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©2016 Integrated Device Technology, Inc.
October 20, 2016
8P34S2108 Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value
of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental.
When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the
fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Figure 2. Additive Phase Jitter. Frequency: 156.25MHz, Integration range: 12kHz to 20MHz = 45fs typical
As with most timing specifications, phase noise measurements have issues relating to the limitations of the measurement equipment. The
noise floor of the equipment can be higher or lower than the noise floor of the device. Additive phase noise is dependent on both the
noise floor of the input source and measurement equipment.
Measured using a Wenzel 156.25MHz Oscillator as the input source.
Offset from Carrier Frequency (Hz)



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