IRFU3707ZPbF datasheet(8/12 Pages) INFINEON

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IRFR/U3707ZPbF

2016-5-31

Power MOSFET Selection for Non-Isolated DC/DC Converters

Control FET

Special attention has been given to the power losses in

the switching elements of the circuit - Q1 and Q2. Power

losses in the high side switch Q1, also called the Control

FET, are impacted by the Rds(on) of the MOSFET, but

these conduction losses are only about one half of the

total losses.

Power losses in the control switch Q1 are given by;

Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput

This can be expanded and approximated by;

This simplified loss equation includes the terms Qgs2 and

Qoss which are new to Power MOSFET data sheets.

Qgs2 is a subelement of traditional gate-source charge

that is included in all MOSFET data sheets. The importance of

splitting this gate-source charge into two sub elements,

Qgs1 and Qgs2, can be seen from Fig 16.

Qgs2 indicates the charge that must be supplied by the

gate driver between the time that the threshold voltage

has been reached and the time the drain current rises to

Id max at which time the drain voltage begins to change.

Minimizing Qgs2 is a critical factor in reducing switching

losses in Q1.

Qoss is the charge that must be supplied to the output

capacitance of the MOSFET during every switching cycle.

Figure A shows how Qoss is formed by the parallel combination

of the voltage dependent (non-linear) capacitance’s Cds

and Cdg when multiplied by the power supply input buss

voltage.

loss  Irms

2  R

ds(on)





 I 

 V

in  f











 I 

gs2

 V

in  f













 Q

g  Vg  f



 Qoss

V

in  f









Synchronous FET

The power loss equation for Q2 is approximated by;

*dissipated primarily in Q1

For the synchronous MOSFET Q2, Rds(on) is an important

characteristic; however, once again the importance of

gate charge must not be overlooked since it impacts

three critical areas. Under light load the MOSFET must

still be turned on and off by the control IC so the gate

drive losses become much more significant. Secondly,

the output charge Qoss and reverse recovery charge Qrr

both generate losses that are transferred to Q1 and in-

crease the dissipation in that device. Thirdly, gate charge

will impact the MOSFETs’ susceptibility to Cdv/dt turn on.

The drain of Q2 is connected to the switching node of the

converter and therefore sees transitions between ground

and Vin. As Q1 turns on and off there is a rate of change

of drain voltage dV/dt which is capacitive coupled to the

gate of Q2 and can induce a voltage spike on the gate

that is sufficient to turn the MOSFET on, resulting in

shoot-through current . The ratio of Qgd/Qgs1 must be min-

imized to reduce the potential for Cdv/dt turn on.

Figure A: Qoss Characteristic

loss  Pconduction  Pdrive  Poutput

loss  Irms

2  R

ds(on)



 Q

g  Vg  f



 Qoss

V

in  f











 Q

rr  Vin  f





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