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STM32L051C8 Datasheet(PDF) 18 Page - STMicroelectronics

Part # STM32L051C8
Description  Access line ultra-low-power 32-bit MCU ARM-based Cortex-M0, up to 64 KB Flash, 8 KB SRAM, 2 KB EEPROM, ADC
PDF  127 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L051C8 Datasheet(HTML) 18 Page - STMicroelectronics

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Functional overview
STM32L051x6 STM32L051x8
18/127
DocID025938 Rev 6
3.2
Interconnect matrix
Several peripherals are directly interconnected. This allows autonomous communication
between peripherals, thus saving CPU resources and power consumption. In addition,
these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power
run, Low-power sleep and Stop modes.
Consumption
VDD=1.8 to 3.6 V
(Typ)
Down to
140 µA/MHz
(from Flash
memory)
Down to
37 µA/MHz
(from Flash
memory)
Down to
8 µA
Down to
4.5 µA
0.4 µA (No
RTC) VDD=1.8 V
0.28 µA (No
RTC) VDD=1.8 V
0.8 µA (with
RTC) VDD=1.8 V
0.65 µA (with
RTC) VDD=1.8 V
0.4 µA (No
RTC) VDD=3.0 V
0.29 µA (No
RTC) VDD=3.0 V
1 µA (with RTC)
VDD=3.0 V
0.85 µA (with
RTC) VDD=3.0 V
1. Legend:
“Y” = Yes (enable).
“O” = Optional can be enabled/disabled by software)
“-” = Not available
2. Some peripherals with wakeup from Stop capability can request HSI to be enabled. In this case, HSI is woken up by the
peripheral, and only feeds the peripheral which requested it. HSI is automatically put off when the peripheral does not need
it anymore.
3. UART and LPUART reception is functional in Stop mode. It generates a wakeup interrupt on Start. To generate a wakeup
on address match or received frame event, the LPUART can run on LSE clock while the UART has to wake up or keep
running the HSI clock.
4. I2C address detection is functional in Stop mode. It generates a wakeup interrupt in case of address match. It will wake up
the HSI during reception.
Table 5. Functionalities depending on the working mode
(from Run/active down to standby) (continued)(1)
IPs
Run/Active
Sleep
Low-
power
run
Low-
power
sleep
Stop
Standby
Wakeup
capability
Wakeup
capability
Table 6. STM32L0xx peripherals interconnect matrix
Interconnect
source
Interconnect
destination
Interconnect action
Run Sleep
Low-
power
run
Low-
power
sleep
Stop
COMPx
TIM2,TIM21,
TIM22
Timer input channel,
trigger from analog
signals comparison
YY
Y
Y
-
LPTIM
Timer input channel,
trigger from analog
signals comparison
YY
Y
Y
Y
TIMx
TIMx
Timer triggered by other
timer
YY
Y
Y
-



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