IR35201MTYPBF datasheet(39/60 Pages) IRF

39 / 60 page

8+0/7+1/6+2 Dual Output Digital Multi-Phase Controller

IR35201

February 8, 2015 | V1.6

I_CRITICAL has a 5% hysteresis level and the

VR_HOT_ICRIT pin will de-assert when the average

output current level drops below 95% of the programmed

current level threshold.

Input Over-voltage Protection

The IR35201 offers protection against input supply over-

voltage. When enabled (Table 39), the VINSEN pin is

compared to a fixed threshold of 14.5V with a 14:1

divider, and shuts down the IC if the threshold is

exceeded.

TABLE 39: INPUT OVER-VOLTAGE OPTIONS

disabled

enabled

Phase Faults

The IR35201 can detect and declare a phase fault when

the current in one or more phases is too high or too low.

It detects the fault when the duty cycle of a particular

phase is 5% higher or lower than the average duty cycle

of all the phases. This feature helps detect severe

imbalances in the phase currents, an unpowered or

damaged MOSFET driver, or a phase that is

disconnected from Vin. The phase fault feature can be

enabled or disabled through an MTP bit. When a phase

fault occurs, the controller shuts down the loop where the

fault occurred, and sets register bits to display which

phase had the fault and whether it faulted high or low.

The phase fault registers are cleared via a register bit

and the VR will restart once ENABLE or Vcc is cycled.

TABLE 40: PHASE CURRENT FAULT REGISTERS

Function

pi_fault_en

Enables phase current fault

shutdown.

clear_phase_faults

Clears all phase faults for each loop.

pi_fault

Indicates which phase has a phase

current fault. 0 – phase1, 1 – phase2,

2 – phase3, 3 – phase4…7-phase 8

max_cond

Indicates one or more phase currents

are too high.

min_cond

Indicates one or more phase currents

are too low.

I2C/PMBUS COMMUNICATION

The IR35201 simultaneously supports I2C and PMBus

through the use of exclusive addressing. This means that

a motherboard PMBus master may communicate with as

many as 127 IR35201-based VRs. Optionally, a resistor

offset can be enabled as shown in Table 41

(note that a 0.01µF capacitor is required across the

resistor per Figure 44), with the offsets shown in

Table 42.

As an example, setting a base 7-bit I2C address of 28h

with a resistor offset of +15 sets the 7-bit I2C address to

37h. Similarly setting a base 7-bit PMBus address of 40h

with a resistor offset of +15 sets the 7-bit PMBus address

to 4Fh.

The IR35201 can also set the I2C address indepen-

dently from the PMBus address. By using a 7-bit address

the user can configure the device to any one of 127

different I2C addresses.

Once the address of the IR35201 is set, it is locked to

protect it from being overridden.

For default programmed devices, the I2C/PMBus

address can be temporarily forced to address 0Ah for

I2C and 0Dh for PMBus by setting EN=VR_HOT=low.

TABLE 41: I2C OFFSET OPTIONS

Enable_I2C

Addr_Offset MTP bit

I2C Address Offset

disabled

enabled

TABLE 42: ADDR RESISTOR OFFSET

ADDR Resistor

I2C Address

Offset

0.845kΩ

1.30kΩ

1.78kΩ

2.32kΩ

2.87kΩ

3.48kΩ

4.12kΩ

4.75kΩ

5.49kΩ

6.19kΩ

6.98kΩ

+10

7.87kΩ

+11

8.87kΩ

+12

10.00kΩ

+13

11.00kΩ

+14

12.10kΩ

+15

Note: Extends the range of PMBus addresses.

IR35201MTYPBF Datasheet(PDF) 39 Page - International Rectifier

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