IR35201MTYPBF datasheet(13/60 Pages) IRF

13 / 60 page

8+0/7+1/6+2 Dual Output Digital Multi-Phase Controller

IR35201

February 8, 2015 | V1.6

GENERAL DESCRIPTION

The IR35201 is a flexible, dual-loop, digital multiphase

PWM buck controller optimized to convert a 12V input

supply to the core voltage required by Intel high

performance microprocessors and DDR memory. It is

easily configurable for 1 to 8 phases of operation on

Loop #1 and 0 to 2 phase operation on Loop #2.

However, at a single time, a total of only 8 phases can

be in operation.

The unique partitioning of analog and digital circuits

within the IR35201 provides the user with easy

configuration capability while maintaining the required

accuracy and performance. Access to on-chip Multiple

Time Programming memory (MTP) to store the

IR35201 configuration parameters enables power

supply designers to optimize their designs without

changing external components.

OPERATING MODES

The IR35201 can be used for Intel

® VR12, VR12.5,

IMVP8 designs, AMD SVI2, and DDR Memory

designs without significant changes to the external

components (Bill of Materials). The required mode is

selected in MTP and the pin-out, VID table and

relevant functions are automatically configured. This

greatly reduces time-to-market and eliminates the

need to manage and inventory different PWM

controllers.

DIGITAL CONTROLLER & PWM

A linear Proportional-Integral-Derivative (PID)

digital controller provides the loop compensation for

system regulation. The digitized error voltage from

the high-speed voltage error ADC is processed by the

digital compensator. The digital PWM generator uses

the outputs of the PID and the phase current balance

control signals to determine the pulse width for

each phase on each loop. The PWM generator has

enough resolution to ensure that there are no limit

cycles. The compensator coefficients are user

configurable to enable optimized system response.

The compensation algorithm uses a PID with two

additional programmable poles. This provides the

digital equivalent of a Type III analog compensator.

ADAPTIVE TRANSIENT ALGORITHM (ATA)

Dynamic load step-up and load step-down transients

require fast system response to maintain the output

voltage within specification limits. This is achieved by

a unique adaptive non-linear digital transient control

loop based on a proprietary algorithm.

MULTIPLE TIME PROGRAMMING MEMORY

The multiple time programming memory (MTP) stores

the device configuration. At power-up, MTP contents

are transferred to operating registers for access

during device operation. MTP allows customization

during both design and high-volume manufacturing.

MTP integrity is verified by Cyclic Redundancy Code

(CRC) checking on each power up. The controller will

not start up in the event of a CRC error.

The IR35201 offers up to 6 writes to configure basic

device parameters such as frequency, fault operation

characteristics, and boot voltage. This represents a

significant size and component saving compared to

traditional analog methods. The following pseudo-

code illustrates how to write the MTP:

# write data

Set MTP Command Register = WRITE,

Line Pointer = An unused line

Poll MTP Command Register until Operation = IDLE.

# verify data was written correctly

Issue a READ Command; then poll OTP Operation Register

till Operation = IDLE

Verify that the Read Succeeded

INTERNAL OSCILLATOR

The IR35201 has a single 96MHz internal oscillator

that generates all the internal system clock

frequencies required for proper device function. The

oscillator frequency is factory trimmed for precision,

and has extremely low jitter (Figure 4) even in light-

load mode (Figure 5). A single internal oscillator is

used to set the switching frequency on each loop

independently.

IR35201MTYPBF Datasheet(PDF) 13 Page - International Rectifier

IR35201MTYPBF Datasheet(HTML) 13 Page - International Rectifier

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