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AS29F010 Datasheet(PDF) 6 Page - Micross Components |
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AS29F010 Datasheet(HTML) 6 Page - Micross Components |
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6 / 26 page ![]() FLASH AS29F010 Micross Components reserves the right to change products or specifications without notice. 6 AS29F010 Rev. 2.6 11/10 power-down. The command register and all internal program/ erase circuits are disabled, and the device resets. Subsequent writes are ignored until V CC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5ns (typical) on OE\, CE\, or WE\ do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE\ = V IL, CE\ = VIH or WE\ = VIH. To initiate a write cycle, CE\ and WE\ must be a logical zero while OE\ is a logical one. Power-Up Write Inhibit If WE\ = CE\ = V IL and OE\ = VIH during power up, the device does not accept commands on the rising edge of WE\. The internal state machine is automatically reset to reading array data on power-up. COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register com- mand sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE\ or CE\, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section. TABLE 3: Autoselect Codes (High Voltage Method) DESCRIPTION CE\ OE\ WE\ A16 to A14 A13 to A10 A9 A8 to A7 A6 A5 to A2 A1 A0 DQ7 to DQ0 Manufacturer ID L L H X X VID XL XL L 01h Device ID L L H X X VID XL XL H 20h 01h (protected) 00h (unprotected) LX H L SA X VID X Sector Protection Verification LL H NOTE: L = Logic Low = V IL, H = Logic High = VIH, SA = Sector Address, X = Don’t Care Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next. See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parameters, and the Read Operation Timings diagram shows the timing diagram. Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this com- mand. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data. Once programming begins, however, the device ignores reset com- mands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the au- toselect mode, the reset command must be written to return to reading array data. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data. |
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