LAN83C185 datasheet(21/60 Pages) SMSC

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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)

Datasheet

SMSC LAN83C185

Revision 0.8 (06-12-08)

DATASHEET

4.3.8

Receiver Errors

During a frame, unexpected code-groups are considered receive errors. Expected code groups are the

DATA set (0 through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the RX_ER

signal is asserted and arbitrary data is driven onto the RXD[3:0] lines. Should an error be detected

during the time that the /J/K/ delimiter is being decoded (bad SSD error), RX_ER is asserted true and

the value ‘1110’ is driven onto the RXD[3:0] lines. Note that the Valid Data signal is not yet asserted

when the bad SSD error occurs.

4.3.9

100M Receive Data across the MII

The 4-bit data nibbles are sent to the MII block. These data nibbles are clocked to the controller at a

rate of 25MHz. The controller samples the data on the rising edge of RX_CLK. To ensure that the

setup and hold requirements are met, the nibbles are clocked out of the PHY on the falling edge of

RX_CLK. RX_CLK is the 25MHz output clock for the MII bus. It is recovered from the received data

to clock the RXD bus. If there is no received signal, it is derived from the system reference clock

(CLKIN).

When tracking the received data, RX_CLK has a maximum jitter of 0.8ns (provided that the jitter of the

input clock, CLKIN, is below 100ps).

4.4

10Base-T Transmit

Data to be transmitted comes from the MAC layer controller. The 10Base-T transmitter receives 4-bit

nibbles from the MII at a rate of 2.5MHz and converts them to a 10Mbps serial data stream. The data

stream is then Manchester-encoded and sent to the analog transmitter, which drives a signal onto the

twisted pair via the external magnetics.

The 10M transmitter uses the following blocks:

MII (digital)

TX 10M (digital)

10M Transmitter (analog)

10M PLL (analog)

4.4.1

10M Transmit Data across the MII

The MAC controller drives the transmit data onto the TXD BUS. When the controller has driven TX_EN

high to indicate valid data, the data is latched by the MII block on the rising edge of TX_CLK. The data

is in the form of 4-bit wide 2.5MHz data.

In order to comply with legacy 10Base-T MAC/Controllers, in Half-duplex mode the PHY loops back

the transmitted data, on the receive path. This does not confuse the MAC/Controller since the COL

signal is not asserted during this time. The PHY also supports the SQE (Heartbeat) signal. See Section

5.4.2, "Collision Detect," on page 43 for more details.

4.4.2

Manchester Encoding

The 4-bit wide data is sent to the TX10M block. The nibbles are converted to a 10Mbps serial NRZI

data stream. The 10M PLL locks onto the external clock or internal oscillator and produces a 20MHz

clock. This is used to Manchester encode the NRZ data stream. When no data is being transmitted

(TX_EN is low, the TX10M block outputs Normal Link Pulses (NLPs) to maintain communications with

the remote link partner.

4.4.3

10M Transmit Drivers

The Manchester encoded data is sent to the analog transmitter where it is shaped and filtered before

being driven out as a differential signal across the TXP and TXN outputs.

LAN83C185 Datasheet(PDF) 21 Page - SMSC Corporation

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