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SST25VF064C Datasheet(PDF) 4 Page - Microchip Technology |
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SST25VF064C Datasheet(HTML) 4 Page - Microchip Technology |
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4 / 37 page ![]() ©2015 Silicon Storage Technology, Inc. DS20005036C 04/15 4 64 Mbit SPI Serial Dual I/O Flash SST25VF064C EOL Data Sheet Pin Description Figure 2: Pin Assignments for 16-Lead SOIC, 8-Contact WSON, and 8-Lead SOIC Table 1: Pin Description Symbol Pin Name Functions SCK Serial Clock To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. SI Serial Data Input To transfer commands, addresses, or data serially into the device. Inputs are latched on the rising edge of the serial clock. SO Serial Data Output To transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. SIO[0:1] Serial Data Input/ Output for Dual I/ O Mode To transfer commands, addresses, or data serially into the device, or data out of the device. Inputs are latched on the rising edge of the serial clock. Data is shifted out on the falling edge of the serial clock. These pins are for Dual I/O mode. CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of any command sequence. WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register. RST#/HOLD# Reset To reset the operation of the device and the internal logic. The device pow- ers on with RST# pin functionality as default. Hold To temporarily stop serial communication with SPI Flash memory while device is selected. This is selected by an instruction sequence. See “Reset/ Hold Mode” page 5 for details. VDD Power Supply To provide power supply voltage: 2.7-3.6V VSS Ground T1.0 25036 SCK SI/SIO0 NC NC NC NC VSS WP# RST#/HOLD# VDD NC NC NC NC CE# SO/SIO1 1392 16-SOIC P1.0 Top View 1392 8-WSON P1.0 1 2 3 4 8 7 6 5 CE# SO/SIO1 WP# VSS Top View VDD RST#/HOLD# SCK SI/SIO0 1392 8-soic S3A P3.1 1 2 3 4 8 7 6 5 CE# SO/SIO1 WP# VSS VDD RST#/HOLD# SCK SI/SIO0 Top View |
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