+

–

+

–

+

–

+

+

SDZ

MUTE

TTL

Buffer

Gain

Control

GAIN

OUTPR_FB

RINP

RINN

Gain

Control

OUTPNR_FB

FAULTZ

SYNC

GAIN/SLV

AM<2:0>

PLIMIT

AVCC

GVDD

LDO

Regulator

LINP

LINN

GND

Input

Sense

PBTL

Select

OUTPL_FB

Gain

Control

OUTNL_FB

AVDD

GVDD

PLIMIT

Reference

Ramp

Generator

Biases and

References

Startup Protection

Logic

SC Detect

DC Detect

Thermal

Detect

UVLO/OVLO

PVCC

GVDD

PVCC

Gate

Drive

OUTNL_

FB

PVCC

GVDD

PVCC

Gate

Drive

PWM

Logic

Modulation and

PBTL Select

OUTPL_FB

GND

OUTPL

BSPL

GND

OUTNL

BSNL

GND

BSNR

OUTPR

GND

OUTNR

OUTNR_

FB

BSPR

OUTPR_FB

PVCC

GVDD

PVCC

Gate

Drive

PVCC

GVDD

PVCC

Gate

Drive

PWM

Logic

Modulation and

PBTL Select

PLIMIT

PLIMIT

+

–

+

–

+

–

+

–

+

–

+

–

–

–

Thermal

Pad

+

–

PVCC

PVCC

Copyright © 2016, Texas Instruments Incorporated

Input

Sense

MONO

Select

11

TPA3128D2

www.ti.com

SLOS941A – MAY 2016 – REVISED DECEMBER 2016

Product Folder Links: TPA3128D2

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Copyright © 2016, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The TPA3128D2 device is a highly efficient Class D audio amplifier with extreme low idle power dissipation. It

can support as low as 23mA idle loss current using standard LC filter configurations. It is integrated with 90-mΩ

MOSFET that allows output currents up to 7.5 A. The high efficiency allows the amplifier to provide an excellent

audio performance without the requirement for a bulky heat sink.

The device can be configured for either master or slave operation by using the SYNC pin. Configuring using the

SYNC pin helps to prevent audible beats noise.

7.2 Functional Block Diagram