MCP37231 datasheet(39/144 Pages) MICROCHIP

39 / 144 page

 2014-2016 Microchip Technology Inc.

DS20005322D-page 39

MCP37231/21-200 AND MCP37D31/21-200

4.0

THEORY OF OPERATION

The

MCP37231/21-200

and

MCP37D31/21-200

device family is a low-power, 16-/14-bit, 200 Msps

Analog-to-Digital Converter (ADC) with built-in features

including Harmonic Distortion Correction (HDC), DAC

Noise Cancellation (DNC), Dynamic Element Matching

(DEM) and flash error calibration.

Depending on the product number selection, the device

offers various built-in digital signal post-processing

features, such as FIR decimation filters, Digital Down-

Conversion (DDC), Fractional Delay Recovery (FDR),

continuous CW beamforming and digital gain and

offset correction. These built-in advanced digital signal

post-processing sub-blocks, which are individually

controlled, can be used for various special applications

such as I/Q demodulation, digital down-conversion,

and ultrasound imaging.

When the device is first powered-up, it performs inter-

nal calibrations by itself and runs with default settings.

From this point, the user can configure the device reg-

isters using the SPI command.

In multi-channel mode, the input channel selection and

MUX scan order are user-configurable, and the inputs

are sequentially multiplexed by the input MUX defined

by the scan order.

The device samples the analog input on the rising edge

of the clock. The digital output code is available after

28 clock cycles of data latency. Latency will increase if

any of the various digital signal post-processing

(DSPP) options are enabled.

The output data can be coded in two’s complement or off-

set binary format, and randomized using the user option.

Data can be output using either the CMOS or LVDS (Low-

Voltage Differential Signaling) interface. Serialized LVDS

output is also available in 16-bit octal-channel mode. In

this mode, each input channel is output serially over a

unique LVDS pair.

4.1

ADC Core Architecture

Figure 4-1 shows the simplified block diagram of the

ADC core. The first stage consists of a 17-level flash

ADC, multi-level Digital-to-Analog Converter (DAC)

and a residue amplifier with a gain of 8. Stages 2 to 6

consist of a 9-level (3-bit) flash ADC, multi-level DAC

and a residue amplifier with a gain of 4. The last stage

is a 9-level 3-bit flash ADC. Dither is added in each of

the first three stages.The digital outputs from all seven

stages are combined in a digital error correction logic

block and digitally processed for the final output.

The first three stages include patented digital

calibration features:

• Harmonic Distortion Correction (HDC) algorithm

that digitally measures and cancels ADC errors

arising from distortions introduced by the residue

amplifiers

• DAC Noise Cancellation (DNC) algorithm that

corrects DAC’s nonlinearity errors

• Dynamic Element Matching (DEM) which

randomizes DAC errors, thereby converting

harmonic distortion to white noise

These digital correction algorithms are first applied

during the Power-on Reset sequence and then operate

in the background during normal operation of the

pipelined ADC. These algorithms automatically track

and correct any environmental changes in the ADC.

More details of the system correction algorithms are

shown in Section 4.13 “System Calibration”.

FIGURE 4-1:

ADC Core Block Diagram.

Clock Generation

Pipeline

(3-bit)

Stage 1

Pipeline

(2-bit)

Stage 2

Pipeline

(2-bit)

Stage 3

Pipeline

(2-bit)

Stage 4

Pipeline

(2-bit)

Stage 5

Pipeline

Stage 6

3-bit Flash

(3-bit)

Stage 7

Digital Error Correction

MUX

Input

AIN0+

AIN0-

HDC1, DNC1

HDC2, DNC2

HDC3, DNC3

(2-bit)

AIN7+

AIN7-

User-Programmable Options

Programmable Digital Signal Post-Processing (DSPP)

Reference Generator

REF0

REF1

REF0

REF1

16-Bit Digital Output

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