MCP37231 datasheet(49/144 Pages) MICROCHIP

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DS20005322D-page 49

MCP37231/21-200 AND MCP37D31/21-200

4.7.1

USING DLL MODE

Using the DLL block is the best option when output

clock phase control is needed while the clock multipli-

cation and digital decimation are not required. When

the DLL block is enabled, the user can control the input

clock Duty Cycle Correction (DCC) and the output

clock phase delay.

See the DLL block in Figure 4-11 for details. Table 4-5

summarizes the DLL control register bits. In addition,

see Table 4-21 for the output clock phase control.

4.7.1.1

Input Clock Duty Cycle Correction

The ADC performance is sensitive to the clock duty

cycle. The ADC achieves optimum performance with

50% duty cycle, and all performance characteristics are

ensured when the duty cycle is 50% with ±1%

tolerance.

When CLK_SOURCE = 0, the external clock is used

as the sampling frequency (fS) of the ADC core. When

the external input clock is not high-quality (for example,

duty cycle is not 50%), the user can enable the internal

clock duty cycle correction circuit by setting the

EN_DUTY bit in Address 0x52 (Register 5-7). When

duty cycle correction is enabled (EN_DUTY=1), only

the falling edge of the clock signal is modified (rising

edge is unaffected).

Because the duty cycle correction process adds addi-

tional jitter noise to the clock signal, this option is rec-

ommended only when an asymmetrical input clock

source causes significant performance degradation or

when the input clock source is not stable.

4.7.1.2

DLL Block Reset Event

The DLL must be reset if the clock frequency is

changed. The DLL reset is controlled by using the

RESET_DLL bit in Address 0x52 (Register 5-7). The

DLL has an automatic reset with the following events:

• During power-up: Stay in reset until the

RESET_DLL bit is cleared.

• When a SOFT_RESET command is issued while

the DLL is enabled: the RESET_DLL bit is

automatically cleared after reset.

4.7.2

USING PLL MODE

The PLL block is mainly used when clock multiplication

is needed. When CLK_SOURCE = 1, the sampling

frequency (fS) of the ADC core is coming from the

internal PLL block.

The recommended PLL output clock range is from

80 MHz to 250 MHz. The external clock input is used

as the PLL reference frequency. The range of the clock

input frequency is from 5 MHz to 250 MHz.

4.7.2.1

PLL Output Frequency and Output

Control Parameters

The internal PLL can provide a stable timing output

ranging from 80 MHz to 250 MHz. Figure 4-11 shows the

PLL block using a charge-pump-based integer N PLL

TABLE 4-5:

DLL CONTROL REGISTER BITS

Control Parameter

Descriptions

CLK_SOURCE

0x53

CLK_SOURCE = 0: external clock input becomes input of the DLL block

EN_DUTY

0x52

Input clock duty cycle correction control bit(1)

EN_DLL

0x52

EN_DLL = 1: enable DLL block

EN_DLL_DCLK

0x52

DLL output clock enable bit

EN_PHDLY<2:0>

0x52

Phase delay control bits of digital output clock (DCLK) when DLL or

decimation filter is used(2)

RESET_DLL

0x52

Reset control bit for the DLL block

Note 1:

Duty cycle correction is not recommended when a high-quality external clock is used.

If decimation is used, the output clock phase delay is controlled using DCLK_PHDLY_DEC<2:0> in

Address 0x64.

Note: The clock duty cycle correction is only

applicable when the DLL block is enabled

(EN_DLL = 1). It is not applicable for the PLL

output.

Note:

The PLL mode is only supported for

sampling frequencies between 80 MHz

and 250 MHz.

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