TABLE 1. FPD87310 Programmable Register Definition (Continued)

Control

Registers

EEPROM

Address

The CONTROL REGISTER provide more setting information to the

input and output interfaces.

General

Purpose Output

GPO Registers

(10 sets)

See Table 2

EEPROM

Memory Map

GPO[0]:a=08B

H

GPO[1]:a=094

H

GPO[2]:a=09D

H

GPO[3]:a=0A6

H

GPO[4]:a=0AF

H

GPO[5]:a=0B8

H

GPO[6]:a=0C1

H

GPO[7]:a=0CA

H

GPO[8]:a=0D3

H

GPO[9]:a=0DC

H

The GPO registers provide complete control over placement of control edges/strobes within

the data frame.

The GPO timing registers (Vertical Start, Vertical Duration, Horizontal Start, and Horizontal

Duration) define the control timing relative to the Internal line and pixel counters.

The line counter corresponds to the line being displayed. The pixel counter corresponds to

the pixel output each line. The Control Register provides polarity selection and/or

generation of a line to line frame to frame alternating signal (REV). Each General Purpose

Output can be uniquely configured.

See the GPO programming examples for details.

- GPO[0]: provides for the data inverting function enabled by bit [3] of the Output Format

Control Register.

- GPO[9]: provides programmable data and clock blanking.

Horizontal Start

(11 bits)

(a+1), (a)

Internal count (pixel counter) at which GPO[x] goes active

Horizontal

Duration

(11 bits)

(a+3), (a+2)

# Pixel Clocks GPO[x] is active after Horizontal Start (if “0”, Horizontal component is always

on)

Vertical Start

(11 bits)

(a+5), (a+4)

Line# at which GPO[x] control generation begins

Vertical Duration

(11 bits)

(a+7), (a+6)

# Lines GPO[x] control generation continues (if “0”, Vertical component is always on)

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