ADE9078ACPZ datasheet(100/108 Pages) AD

100 / 108 page

Data Sheet

ADE9078

Rev. 0| Page 99 of 107

Addr. Name

Bits

Bit Name

Settings Description

Reset

Access

0x481 CONFIG1

EXT_REF

Set this bit if using an external voltage reference.

0x0

R/W

[14:13] RESERVED

Reserved.

0x0

IRQ0_ON_IRQ1

Set this bit to combine all the interrupts onto a

single interrupt pin, IRQ1, instead of using two

pins, IRQ0 and IRQ1. Note that the IRQ0 pin still

indicates the enabled IRQ0 events while in this

mode and the IRQ1 indicates both IRQ1 and IRQ0

events.

0x0

R/W

BURST_EN

Set this bit to enable burst read functionality on

the registers from Address 0x500 to Address 0x6FF.

Note that this bit disables the CRC being

appended to SPI register reads.

0x0

R/W

RESERVED

Reserved.

0x0

[9:8]

PWR_SETTLE

These bits configure the time for the power and

filter based rms measurements to settle before

starting the power, energy and CF accumulations.

0x0

R/W

0: 64 ms.

1: 128 ms.

2: 256 ms.

3: 0 ms.

[7:6]

RESERVED

Reserved.

0x0

CF_ACC_CLR

Set this bit to clear the accumulation in the digital

to frequency converter and CFDEN counter. Note

that this bit automatically clears itself.

0x0

RESERVED

Reserved.

0x0

[3:2]

CF4_CFG

These bits select which function to output on the

CF4 pin.

0x0

R/W

00 CF4, from digital to frequency converter.

01 CF4, from digital to frequency converter.

10 EVENT.

11 DREADY.

CF3_CFG

This bit selects which function to output on the

CF3 pin.

0x0

R/W

0 CF3, from digital to frequency converter.

1 Zero Crossing output selected by the ZX_SEL bits

in the ZX_LP_SEL register.

SWRST

Set this bit to initiate a software reset. Note that

this bit is self clearing.

0x0

0x490 CFMODE

CF4DIS

CF4 output disable. Set this bit to disable the CF4

output and bring the pin high. Note that when this

bit is set, the CFx bit in STATUS0 is not set when a

CF pulse is accumulated in the digital to frequency

converter.

0x0

R/W

CF3DIS

CF3 output disable--see CF4DIS.

0x0

R/W

CF2DIS

CF2 output disable--see CF4DIS.

0x0

R/W

CF1DIS

CF1 output disable--see CF4DIS

0x0

R/W

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