DS2196L datasheet(41/157 Pages) DALLAS

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DS2196

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CCR2B: COMMON CONTROL REGISTER 2 FRAMER B (Address = D8 Hex)

(MSB)

(LSB)

TFM

TB8ZS

TSLC96

TZSE

RFM

RB8ZS

RSLC96

RFDL

SYMBOL

POSITION

NAME AND DESCRIPTION

TFM

CCR2B.7

Transmit Frame Mode Select.

0 = D4 framing mode

1 = ESF framing mode

TB8ZS

CCR2B.6

Transmit B8ZS Enable.

0 = B8ZS disabled

1 = B8ZS enabled

TSLC96

CCR2B.5

Transmit SLC–96 / Fs–Bit Insertion Enable. Only set this

bit to a 1 in D4 framing applications. Must be set to 1 to source

the Fs pattern. See Section 18 for details.

0 = SLC–96/Fs–bit insertion disabled

1 = SLC–96/Fs–bit insertion enabled

TZSE

CCR2B.4

Transmit FDL Zero Stuffer Enable. Set this bit to 0 if using

the internal HDLC/BOC controller instead of the legacy support

for the FDL. See Section 18 for details.

0 = zero stuffer disabled

1 = zero stuffer enabled

RFM

CCR2B.3

Receive Frame Mode Select.

0 = D4 framing mode

1 = ESF framing mode

RB8ZS

CCR2B.2

Receive B8ZS Enable.

0 = B8ZS disabled

1 = B8ZS enabled

RSLC96

CCR2B.1

Receive SLC–96 Enable. Only set this bit to a 1 in D4/SLC–

96 framing applications. See Section 18 for details.

0 = SLC–96 disabled

1 = SLC–96 enabled

RFDL

CCR2B.0

Receive FDL Zero Destuffer Enable. Set this bit to 0 if using

the internal HDLC/BOC controller instead of the legacy support

for the FDL. See Section 18 for details.

0 = zero destuffer disabled

1 = zero destuffer enabled

DS2196L Datasheet(PDF) 41 Page - Dallas Semiconductor

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