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AM29LV800T Datasheet(PDF) 21 Page - Advanced Micro Devices

Part # AM29LV800T
Description  8 Megabit (1,048,576 x 8-Bit/524,288 x 16-Bit) CMOS 3.0 Volt-only, Sectored Flash Memory
PDF  48 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM29LV800T Datasheet(HTML) 21 Page - Advanced Micro Devices

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Am29LV800T/Am29LV800B
21
PRELIMINARY
RESET: Hardware Reset Pin
The RESET pin is an active low signal. A logic ‘0’ on this
pin will force the device out of any mode that is currently
executing back to the reset state. This allows a system
reset to take effect immediately without having to wait for
the device to finish a long execution cycle. To avoid a po-
tential bus contention during a system reset, the device
is isolated from the data I/O bus by tri-stating the data
output pins for the duration of the RESET pulse.
If RESET is asserted during a program or erase oper-
ation, the RY/BY pin will remain low until the reset op-
eration is internally complete. This will require between
1
µs and 20 µs. Hence the RY/BY pin can be used to
signal that the reset operation is complete. Otherwise,
allow for the maximum reset time of 20
µs. If RESET is
asserted when a program or erase operation is not ex-
ecuting (RY/BY pin is high), the reset operation will be
complete within 500 ns.
Asserting RESET during a program or erase operation
leaves erroneous data stored in the address locations
being operated on at the time of device reset. These lo-
cations need updating after the reset operation is com-
plete. See Figure 4 for timing specifications.
The device enters ICC4 standby mode (200 nA) when
VSS ± 0.3 V is applied to the RESET pin.The device can
enter this mode at any time, regardless of the logical
condition of the CE pin. Furthermore, entering ICC4
during a program or erase operation leaves erroneous
data in the address locations being operated on at the
time of the RESET pulse. These locations need updat-
ing after the device resumes standard operations. After
the RESET pin goes high, a minimum latency period of
50 ns must occur before a valid read can take place.
RESET
RY/BY
tRL
20 µs max
20478D-10
Figure 3.
Device Reset During a Program or Erase Operation
0 V
RY/BY
RESET
tRL
20478D-11
Figure 4.
Device Reset During Read Mode



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