AM29LV800T datasheet(23/48 Pages) AMD

23 / 48 page

Am29LV800T/Am29LV800B

PRELIMINARY

Data Protection

The Am29LV800 is designed to offer protection against

accidental erasure or programming caused by spurious

system level signals that may exist during power transi-

tions. During power-up, the device automatically resets

the internal state machine to the read mode. Also, with

its control register architecture, alteration of the mem-

ory contents only occurs after successful completion of

the command sequences.

The Am29LV800 incorporates several features to pre-

vent inadver tent write cycles resulting from VCC

power-up and power-down transitions or system noise.

Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up

and power-down, a write cycle is locked out for VCC

less than VLKO (lock-out voltage). If VCC < VLKO, the

command register is disabled and all internal program/

erase circuits are disabled. Under this condition, the

device will reset to read mode. Subsequent writes will

be ignored until the VCC level is greater than VLKO. It is

the user’s responsibility to ensure that the control levels

are logically correct when VCC is above VLKO (unless

the RESET pin is asserted).

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE, CE, or

WE will not change the command registers.

Logical Inhibit

Writing is inhibited by holding any one of OE = VIL, CE

= VIH, or WE = VIH. To initiate a write, CE and WE must

be logical zero while OE is a logical one.

Power-Up Write Inhibit

Power up of the device with WE = CE = VIL and OE =

VIH will not accept commands on the rising edge of WE.

The internal state machine is automatically reset to

read mode on power up.

AM29LV800T Datasheet(PDF) 23 Page - Advanced Micro Devices