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ESDALC6V1P6 Datasheet(PDF) 7 Page - STMicroelectronics

Part # ESDALC6V1P6
Description  QUAD LOW CAPACITANCE TRANSIL TM ARRAY FOR ESD PROTECTION
PDF  10 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ESDALC6V1P6 Datasheet(HTML) 7 Page - STMicroelectronics

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Figure A9 shows the measurement circuit used to quantify the crosstalk effect in a classical digital
application.
Figure A10 shows that in such a condition, ie signal from 0 to 5V and rise time of a few ns, the impact on
the disturbed line is less than 5 mV peak to peak. No data disturbance was noted on the concerned line.
The measurements performed with falling edges give an impact within the same range.
3. PCB layout recommendations
As ESD is a fast event, the dI/dt caused by this surge is about 30A/ns (risetime=1ns, Ipeak=30A), that
means each nH causes an overvoltage of 30V.
Thus, the circuit board layout is a critical design step in the suppression of ESD induced transients by
reducing parasitic inductances. To ensure that, the following guidelines are recommended :
■ The ESDALC6V1P6 should be placed as close as possible to the input terminals or connectors.
■ The path length between the ESD suppressor and the protected line should be minimized.
■ All conductive loops, including power and ground loops should be minimized.
■ The ESD transient return path to ground should be kept as short as possible.
■ The connections from the ground pins to the ground plane should be the shortest possible.
4. Comparison with varistors
Low leakage current for Transil™ device
■ Improve the autonomy of portable equipments as mobile
Better efficiency in terms of ESD protection by using Transil™ device
■ Varistors are bidirectional devices and so are not suitable to protect sensitive ICs, because they will be
submitted to high voltages in the negative way.
■ Ratio VCL/VBR lower for Transil™ device
■ Less dispersion in terms of VBR
No ageing phenomena regarding ESD events with Transil™ device
■ Higher efficiency in terms of ESD protection
Fig. A9: Digital crosstalk test configuration.
Fig. A10: Typical digital crosstalk response.
Varistors
TRANSIL™
Leakage current
--
+++
Protection efficiency
--
++
Ageing
--
++
GND
I/O4
I/O1
VG1
β21 G1
V
unloaded
unloaded
pulse generator
F= 100kHz
t = 20ns
R
0 - 5V
β21 G1
V
VG1



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