Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

FT313HP-R Datasheet(PDF) 52 Page - Future Technology Devices International Ltd.

Part # FT313HP-R
Description  USB2.0 HS Embedded Host Controller
PDF  67 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  FTDI [Future Technology Devices International Ltd.]
Direct Link  http://www.ftdichip.com
Logo FTDI - Future Technology Devices International Ltd.

FT313HP-R Datasheet(HTML) 52 Page - Future Technology Devices International Ltd.

Back Button FT313HP-R Datasheet HTML 48Page - Future Technology Devices International Ltd. FT313HP-R Datasheet HTML 49Page - Future Technology Devices International Ltd. FT313HP-R Datasheet HTML 50Page - Future Technology Devices International Ltd. FT313HP-R Datasheet HTML 51Page - Future Technology Devices International Ltd. FT313HP-R Datasheet HTML 52Page - Future Technology Devices International Ltd. FT313HP-R Datasheet HTML 53Page - Future Technology Devices International Ltd. FT313HP-R Datasheet HTML 54Page - Future Technology Devices International Ltd. FT313HP-R Datasheet HTML 55Page - Future Technology Devices International Ltd. FT313HP-R Datasheet HTML 56Page - Future Technology Devices International Ltd. Next Button
Zoom Inzoom in Zoom Outzoom out
 52 / 67 page
background image
Copyright © 2013 Future Technology Devices International Limited
52
Document No.: FT_000589
FT313H USB2.0 HS Host Controller Datasheet Version 1.2
Clearance No.: FTDI# 318
6.4.2 DMA timing
DMA timing characteristics (Ambient Temperature = -40°C to +85°C)
Parameter
Description
Min
Max
Unit
Tsudreqdack
DREQ Set-up Time before DACK
Assertion
0
-
ns
Tddackdreq
DACK De-assertion to Next DREQ
Assertion Time
18
-
ns
Thdreqdack
DREQ Hold Time after Last Strobe
Assertion
-
35
ns
Trwp
RD_N/WR_N Pulse Width
40
-
ns
Toe
Data Valid Time after RD_N Assertion
8
-
ns
Trdh
Read Data Hold Time after RD_N De-
asserts
4
9
ns
Twdh
Write Data Hold Time after WR_N De-
assertion
0
-
ns
Tdadvh
Write Data Set-up Time before WR_N
De-assertion
6
-
ns
Tsudackrw
DACK Set-up Time before
RD_N/WR_N Assertion
0
-
ns
Trwdack
DACK De-assertion after RD_N/WR_N
De-assertion
0
-
ns
Tcyc
DMA Read/Write Cycle Time
80
-
ns
Table 6-13 DMA timing
DREQ
DACK
RD_N/
WR_N
DATA[15:0]
(read)
DATA[15:0]
(write)
Tsudreqdack
Tsudackrw
Trwp
Tcyc
Thdreqdack
Tddackdreq
Trwdack
Toe
Trdh
Tdadvh
Twdh
DATA1
DATA2
DATAn
Figure 6-7 DMA read and write



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com