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AS4C32M16SB-7TCN Datasheet(PDF) 29 Page - Alliance Semiconductor Corporation |
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AS4C32M16SB-7TCN Datasheet(HTML) 29 Page - Alliance Semiconductor Corporation |
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29 / 55 page  Figure 24.2. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=3) Hi-Z T0 T1 T2 Don’t Care T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RAx RAx CAx Activate Command Bank A Read Command Bank A Ax0 Ax1 Ax2 Ax3 tHZ Clock Suspend 1 Cycle Clock Suspend 2 Cycles Clock Suspend 3 Cycles CLK CS# CKE RAS# CAS# WE# BA0,1 A10 A0-A9, A11-A12 DQM DQ AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Confidential - 29/55 - Rev.1.0 June 2016 |
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