Copyright 1998 National Semiconductor Corp.

4

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2.0 Pin Description

Table 1:

Pin Description)

PIN NAME

NR

TYPE

DESCRIPTION

SCLK

1

1

OUTPUT/INPUT. CR16A bus interface System CLocK output. In core mode this pin

is input.

VDD

2

Digital supply voltage

VSS

3

Digital ground

4-11

5

TRI-STATE OUTPUT. Programmable Power Down pins 7 to 0 to radio interface.

PD7,6 have 12 mA drive.

RFCLK

12

5b

OUTPUT (Slope controlled). 10.368 MHz clock output. Logic ‘0’ after reset or when

disabled.

MEN1n

13

5

OUTPUT. Programmable Load Enable for synthesizer. Can be synchronized to

LKD input.

SO

14

1

TRI-STATE OUTPUT. Serial data output.

SK

15

5

OUTPUT. Serial interface clock: 1.152 MHz

CMPOUT

16

1

TRI-STATE OUTPUT. Comparator output pin.

RDI

17

analog

INPUT. Received Data. The polarity of this input is programmable.

CMPREF

18

analog

INPUT. Comparator reference level. Internally a six bit DAC can be connected to

this pin to compensate for DC offsets.

RSSI

19

analog

INPUT. Receiver Signal Strength Indication. This signal is connected to a 6-bit ADC

input with peak hold circuitry. PD0 internally controls the peak hold circuitry. If PD0

is low RSSI is sampled, else the RSSI input will be connected to ground.

AVD

20

Analog supply voltage.

AVS

21

Analog ground.

TDO

22

5/analog

TRI-STATE OUTPUT. Transmit Data. The polarity of this output is programmable.

P0[0] or

UTX

23

2

INPUT/OUTPUT with selectable pull up resistor. General purpose memory

mapped I/O port bit. UART data output.

P0[1] or

URX

24

3

INPUT/OUTPUT with selectable pull down resistor. General purpose memory

mapped I/O port bit. UART data input.

P0[2] or

CS0

25

2

INPUT/OUTPUT with selectable pull up resistor. General purpose memory

mapped I/O port bit. Multi function Chip select output CS0

P0[3] or

CS1

26

2

INPUT/OUTPUT with selectable pull up resistor. General purpose memory

mapped I/O port bit. Multi function Chip select output CS1

P0[4] or

CS2

27

2

INPUT/OUTPUT with selectable pull up resistor. General purpose memory

mapped I/O port bit. Multi function Chip select output CS2

P0[5] or

AD18

28

3

INPUT/OUTPUT with selectable pull down resistor. General purpose memory

mapped I/O port bit. OUTPUT Address bit 18.

P0[6] or

AD19

29

3

INPUT/OUTPUT with selectable pull down resistor. General purpose memory

mapped I/O port bit. OUTPUT Address bit 19.

P0[7] or

CLK100

30

2

INPUT/OUTPUT with selectable pull up resistor. General purpose memory

mapped I/O port bit. OUTPUT 100 Hz clock synchronized to 10 msec frame.

P1[0] or

P10_INT

31

2

INPUT/OUTPUT with selectable pull up resistor. General purpose memory

mapped I/O port bit. Level sensitive interrupt source P10_INT

P1[1] or

SCK

32

2

INPUT/OUTPUT with selectable pull up resistor. General purpose memory

mapped I/O port bit. SPI Clock input/output

P1[2] or

SEN

33

2

INPUT/OUTPUT with selectable pull up resistor. General purpose memory

mapped I/O port bit. SPI Clock enable input if SPI slave. If SPI master this pin must

be set/reset by software.

P1[3] or

SDI

34

2

INPUT/OUTPUT with selectable pull up resistor. General purpose memory

mapped I/O port bit. SPI data input

P1[4] or

SDO

35

2

INPUT/OUTPUT with selectable pull up resistor. General purpose memory

mapped I/O port bit. SPI data output