L99MC6GJ datasheet(38/55 Pages) STMICROELECTRONICS

38 / 55 page

SPI control and status register

L99MC6GJ

38/55

DocID026835 Rev 3

9.4.2

Example 2: Bridge mode configuration

From Table 34 and Table 35 follow that the value A8h is written at RAM address 01h

(control register 1).

Table 36

describe more in detail the data byte structure.

Hereafter the actions linked to each value of bit or group of bits:



ENCP = 1

: Charge pump stays activated



CH5[2:0] = 010b

: Channel 5 is on, PWM disabled, overcurrent recovery mode

disabled, low slew rate



BRIDGE_2&5 = 1

: Bridge mode for channel 2 and channel 5 activated



CH2[2:0] = 000b

: Channel 2 is off, open-load detection in off-state disabled

From Table 37 and Table 38 follow that the value 0Ah is written at RAM address 02h

(control register 2).

Table 39

describe more in detail the data byte structure.

Table 34. Command byte 1 - example 2

MSB

LSB

Operating code

Address

Table 35. Data byte 1 - example 2

MSB

LSB

101

Table 36. Data byte description 1 - example 2

ENCP

CH5

[2]

CH5

[1]

CH5

[0]

Bridge

2&5

CH2

[2]

CH2

[1]

CH2

[0]

101

Table 37. Command byte 2 - example 2

MSB

LSB

Operating code

Address

Table 38. Data byte 2 - example 2

MSB

LSB

001

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