 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SPC560P50L5 Datasheet(PDF) 95 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
SPC560P50L5 Datasheet(HTML) 95 Page - STMicroelectronics |
|
|
95 / 112 page  SPC560P44Lx, SPC560P50Lx Electrical characteristics Doc ID 14723 Rev 9 95/112 Figure 28. External interrupt timing 3.17.5 DSPI timing IRQ 2 3 1 Table 42. DSPI timing(1) No. Symbol C Parameter Conditions Value Unit Min Max 1tSCK CC D DSPI cycle time Master (MTFE = 0) 60 — ns Slave (MTFE = 0) 60 — 2tCSC CC D CS to SCK delay — 16 — ns 3tASC CC D After SCK delay — 26 — ns 4tSDC CC D SCK duty cycle — 0.4 * tSCK 0.6 * tSCK ns 5tA CC D Slave access time SS active to SOUT valid — 30 ns 6tDIS CC D Slave SOUT disable time SS inactive to SOUT high impedance or invalid —16 ns 7tPCSC CC D PCSx to PCSS time — 13 — ns 8tPASC CC D PCSS to PCSx time — 13 — ns 9tSUI CC D Data setup time for inputs Master (MTFE = 0) 35 — ns Slave 4 — Master (MTFE = 1, CPHA = 0) 35 — Master (MTFE = 1, CPHA = 1) 35 — 10 tHI CC D Data hold time for inputs Master (MTFE = 0) –5 — ns Slave 4 — Master (MTFE = 1, CPHA = 0) 11 — Master (MTFE = 1, CPHA = 1) –5 — |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
