ST72321R7-Auto datasheet(149/243 Pages) STMICROELECTRONICS

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ST72321xx-Auto

Serial communications interface (SCI)

Doc ID 13829 Rev 1

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15.7.2

Control register 1 (SCICR1)

SCICR1

Reset value: X000 0000 (x0h)

543

SCID

WAKE

PCE

PIE

Table 74.

SCICR1 register description

Bit

Name

Function

7R8

Receive data bit 8

This bit is used to store the 9th bit of the received word when M = 1.

6T8

Transmit data bit 8

This bit is used to store the 9th bit of the transmitted word when M = 1.

5SCID

Disabled for low power consumption

When this bit is set the SCI prescalers and outputs are stopped and the end of the

current byte transfer in order to reduce power consumption.This bit is set and

cleared by software.

0: SCI enabled

1: SCI prescaler and outputs disabled

Word length

This bit determines the word length. It is set or cleared by software.

0: 1 Start bit, 8 Data bits, 1 Stop bit

1: 1 Start bit, 9 Data bits, 1 Stop bit

Note: The M bit must not be modified during a data transfer (both transmission and

reception).

WAKE

Wake-up method

This bit determines the SCI wake-up method. It is set or cleared by software.

0: Idle line

1: Address mark

2PCE

Parity control enable

This bit selects the hardware parity control (generation and detection). When the

parity control is enabled, the computed parity is inserted at the MSB position (9th

bit if M = 1; 8th bit if M = 0) and parity is checked on the received data. This bit is

set and cleared by software. Once it is set, PCE is active after the current byte (in

reception and in transmission).

0: Parity control disabled

1: Parity control enabled

1PS

Parity selection

This bit selects the odd or even parity when the parity generation/detection is

enabled (PCE bit set). It is set and cleared by software. The parity is selected after

the current byte.

0: Even parity

1: Odd parity

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