ST72321R7-Auto datasheet(150/243 Pages) STMICROELECTRONICS

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Serial communications interface (SCI)

ST72321xx-Auto

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Doc ID 13829 Rev 1

15.7.3

Control register 2 (SCICR2)

0PIE

Parity interrupt enable

This bit enables the interrupt capability of the hardware parity control when a parity

error is detected (PE bit set). It is set and cleared by software.

0: Parity error interrupt disabled

1: Parity error interrupt enabled

Table 74.

SCICR1 register description (continued)

Bit

Name

Function

SCICR2

Reset value: 0000 0000 (00h)

543

TIE

TCIE

RIE

ILIE

RWU

SBK

Table 75.

SCICR2 register description

Bit

Name

Function

7TIE

Transmitter interrupt enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR register.

6TCIE

Transmission complete interrupt enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever TC = 1 in the SCISR register.

5RIE

Receiver interrupt enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR

4ILIE

Idle line interrupt enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever IDLE = 1 in the SCISR register.

3TE

Transmitter enable

This bit enables the transmitter. It is set and cleared by software.

0: Transmitter is disabled

1: Transmitter is enabled

Notes:

During transmission, a ‘0’ pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble

(idle line) after the current word.

When TE is set there is a 1 bit-time delay before the transmission starts.

Caution: The TDO pin is free for general purpose I/O only when the TE and RE bits

are both cleared (or if TE is never set).

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