ST72321R7-Auto datasheet(152/243 Pages) STMICROELECTRONICS

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Serial communications interface (SCI)

ST72321xx-Auto

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Doc ID 13829 Rev 1

15.7.6

Extended receive prescaler division register (SCIERPR)

This register allows setting of the extended prescaler rate division factor for the receive

circuit.

Table 76.

SCIBRR register description

Bit

Name

Function

7:6

SCP[1:0]

First SCI Prescaler

These 2 prescaling bits allow several standard clock division ranges.

00:

PR prescaling factor = 1

01:

PR prescaling factor = 3

10:

PR prescaling factor = 4

11:

PR prescaling factor = 13

5:3

SCT[2:0]

SCI Transmitter rate divisor

These 3 bits, in conjunction with the SCP1 and SCP0 bits define the total division

applied to the bus clock to yield the transmit rate clock in conventional Baud Rate

Generator mode.

000: TR dividing factor = 1

001: TR dividing factor = 2

010: TR dividing factor = 4

011: TR dividing factor = 8

100: TR dividing factor = 16

101: TR dividing factor = 32

110: TR dividing factor = 64

111: TR dividing factor = 128

2:0

SCR[2:0]

SCI Receiver rate divisor

These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied

to the bus clock to yield the receive rate clock in conventional Baud Rate

Generator mode.

000: RR dividing factor = 1

001: RR dividing factor = 2

010: RR dividing factor = 4

011: RR dividing factor = 8

100: RR dividing factor = 16

101: RR dividing factor = 32

110: RR dividing factor = 64

111: RR dividing factor = 128

SCIERPR

Reset value: 0000 0000 (00h)

543

ERPR[7:0]

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