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ST72344K2 Datasheet(PDF) 86 Page - STMicroelectronics

Part # ST72344K2
Description  SCI asynchronous serial interface
PDF  247 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72344K2 Datasheet(HTML) 86 Page - STMicroelectronics

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On-chip peripherals
ST72344xx, ST2345xx
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Doc ID 12321 Rev 6
Figure 40.
Window watchdog timing diagram
11.1.6
Low-power modes
T6 bit
Reset
WDGWR
T[5:0] CNT downcounter
time
Refresh Window
Refresh not allowed
(step = 16384/fOSC2)
3Fh
Table 37.
Descriptions
Mode
Description
Slow
No effect on Watchdog: the downcounter continues to decrement at normal speed.
Wait
No effect on Watchdog: the downcounter continues to decrement.
Halt
OIE bit in
MCCSR
register
WDGHALT
bit in
Option Byte
00
No Watchdog reset is generated. The MCU enters Halt
mode. The Watchdog counter is decremented once and
then stops counting and is no longer able to generate a
watchdog reset until the MCU receives an external
interrupt or a reset.
If an interrupt is received (refer to interrupt table mapping
to see interrupts which can occur in halt mode), the
Watchdog restarts counting after 256 or 4096 CPU clocks.
If a reset is generated, the Watchdog is disabled (reset
state) unless Hardware Watchdog is selected by option
byte. For application recommendations see Section 11.1.8
below.
0
1
A reset is generated instead of entering halt mode.
Active-halt
1
x
No reset is generated. The MCU enters Active Halt mode.
The Watchdog counter is not decremented. It stop
counting. When the MCU receives an oscillator interrupt or
external interrupt, the Watchdog restarts counting
immediately. When the MCU receives a reset, the
Watchdog restarts counting after 256 or 4096 CPU clocks.



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