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ST72344S2 Datasheet(PDF) 60 Page - STMicroelectronics

Part # ST72344S2
Description  SCI asynchronous serial interface
PDF  247 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72344S2 Datasheet(HTML) 60 Page - STMicroelectronics

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Interrupts
ST72344xx, ST2345xx
60/247
Doc ID 12321 Rev 6
8.6
External interrupts
8.6.1
I/O port interrupt sensitivity
The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR
register (Figure 24). This control allows to have up to 4 fully independent external interrupt
source sensitivities.
Each external interrupt source can be generated on four (or five) different events on the pin:
●
Falling edge
●
Rising edge
●
Falling and rising edge
●
Falling edge and low level
●
Rising edge and high level (only for ei0 and ei2)
To guarantee correct functionality, the sensitivity bits in the EICR register can be modified
only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that
interrupts must be disabled before changing sensitivity.
The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits
of the EICR.
Figure 24.
External interrupt control bits
IS10
IS11
EICR
SENSITIVITY
CONTROL
PBOR.3
PBDDR.3
IPB BIT
PB3
ei2 INTERRUPT SOURCE
PORT B [3:0] INTERRUPTS
PB3
PB2
PB1
PB0
IS10
IS11
EICR
SENSITIVITY
CONTROL
PBOR.4
PBDDR.4
PB4
ei3 INTERRUPT SOURCE
PORT B4 INTERRUPT
PB4
IS20
IS21
EICR
SENSITIVITY
CONTROL
PAOR.3
PADDR.3
IPA BIT
PA3
ei0 INTERRUPT SOURCE
PORT A3, E1 INTERRUPTS
IS20
IS21
EICR
SENSITIVITY
CONTROL
PFOR.2
PFDDR.2
PF2
ei1 INTERRUPT SOURCE
PORT F [2:0] INTERRUPTS
PF2
PF1
PF0
PE1
PA3



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