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ST72344S2 Datasheet(PDF) 26 Page - STMicroelectronics

Part # ST72344S2
Description  SCI asynchronous serial interface
PDF  247 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72344S2 Datasheet(HTML) 26 Page - STMicroelectronics

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Register and memory map
ST72344xx, ST2345xx
26/247
Doc ID 12321 Rev 6
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
I2C3SNS
I2C3SCR1
I2C3SCR2
I2C3SSR
I2C3SBCR
I2C3SSAR1
I2C3SCAR1
I2C3SSAR2
I2C3SCAR2
I2C3SSAR3
I2C3SCAR3
I2C3SNS Control Register 1
I2C3SNS Control Register 2
I2C3SNS Status Register
I2C3SNS Byte Count Register
I2C3SNS Slave Address 1 Register
I2C3SNS Current Address 1 Register
I2C3SNS Slave Address 2 Register
I2C3SNS Current Address 2 Register
I2C3SNS Slave Address 3 Register
I2C3SNS Current Address 3 Register
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
0070h
0071h
0072h
ADC
ADCCSR
ADCDRH
ADCDRL
A/D Control Status Register
A/D Data Register High
A/D Data Low Register
00h
xxh
0000 00xxb
R/W
Read Only
Read Only
0073h to
007Fh
Reserved area (13 bytes)
1.
x = undefined.
2.
R/W = read/write.
3.
The bits associated with unavailable pins must always keep their reset value.
4.
The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the
I/O pins are returned instead of the DR register contents.
5.
For a description of the Debug Module registers, see ST7 ICC protocol reference manual.
Table 4.
Hardware register map (continued)
Address
Block
Register
label
Register name
Reset status
(1)
Remarks
(2)



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