ST72344S2 datasheet(226/247 Pages) STMICROELECTRONICS

226 / 247 page

Electrical characteristics

ST72344xx, ST2345xx

226/247

Doc ID 12321 Rev 6

Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.

Figure 118. Typical A/D converter application

Note:

CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout

quality) plus the pad capacitance (3 pF). A high CPARASITIC value will downgrade conversion

accuracy. To remedy this, fADC should be reduced.

This graph shows that depending on the input signal variation (fAIN), CAIN can be increased

for stabilization time and decreased to allow the use of a larger serial resistor (RAIN).

Table 113.

ADC characteristics

Symbol

Parameter

Conditions

Min

Typ (1)

Unless otherwise specified, typical data are based on TA= 25 °C and VDD-VSS= 5 V. They are given only

as design guidelines and are not tested.

Max

Unit

fADC

ADC clock frequency

0.4

MHz

VAIN

Conversion voltage range (2)

When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.

VSSA

VDDA

RAIN

External input resistor

10 (3)

Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than

10 k

Ω). Data based on characterization results, not tested in production.

CADC

Internal sample and hold capacitor

tSTAB

Stabilization time after ADC

enable

fCPU = 8 MHz,

fADC = 4 MHz

0 (4)

The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable

is then always valid.

µs

tADC

Conversion time (Sample+Hold)

3.5

– Sample capacitor loading time

– Hold conversion time

1/fADC

IADC

Analog Part

Digital Part

0.2

AINx

ST72XXX

VDD

±1

μA

0.6 V

CADC

6 pF

VAIN

RAIN

10-Bit A/D

Conversion

2 k

Ω (max)

CAIN

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