ST72344S2 datasheet(234/247 Pages) STMICROELECTRONICS

234 / 247 page

Device configuration and ordering information

ST72344xx, ST2345xx

234/247

Doc ID 12321 Rev 6

OPT3 = OSC RC Oscillator selection

0: RC oscillator on

1: RC oscillator off

OPT2 = DIV2EN PLL Divide by 2 enable

0: PLL division by 2 enabled

1: PLL division by 2 disabled

Note:

DIV2EN must be kept disabled when PLLx4 is enabled.

OPT1 = PLLx4x8 PLL Factor selection

0: PLLx4

1: PLLx8

OPT0 = PLLOFF PLL disable

0: PLL enabled

1: PLL disabled (by-passed)

These option bits must be configured as described in Table 122 depending on the voltage

range and the expected CPU frequency.

15.1.3

Option byte 2

Note:

OPT7:0 = Reserved. Must be kept at 1.

Table 121.

Selection of the resonator oscillator range

OSCRANGE

Typical frequency range

with Resonator

1~2 MHz

2~4 MHz

4~8 MHz

8~16 MHz

Reserved

External clock

Table 122.

List of valid option combinations

Target ratio

VDD

Option bits

DIV2 EN

PLL OFF

PLL x4x8

x4 (1)

For a target ratio of x4 between 3.3V - 3.65V, this is the recommended configuration.

2.7 V - 3.65 V

3.3 V - 5.5 V

001

101

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