ST72361AR4-Auto datasheet(66/279 Pages) STMICROELECTRONICS

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Power saving modes

ST72361xx-Auto

66/279

Doc ID 12468 Rev 3

Note:

As soon as active halt is enabled, executing a HALT instruction while the Watchdog is active

does not generate a RESET.

This means that the device cannot spend more than a defined delay in this power saving

mode.

Figure 27.

ACTIVE HALT timing overview

Figure 28.

ACTIVE HALT mode flow-chart

Note:

This delay occurs only if the MCU exits ACTIVE HALT mode by means of a RESET.

Peripheral clocked with an external clock source can still be active.

Only the RTC interrupt and some specific interrupts can exit the MCU from ACTIVE HALT

mode (such as external interrupt). Refer to Table 16 for more details.

Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits in the

CC register are set to the current software priority level of the interrupt routine and restored

when the CC register is popped.

7.6

Auto wake-up from halt mode

Auto Wake-Up From Halt (AWUFH) mode is similar to Halt mode with the addition of an

internal RC oscillator for wake-up. Compared to ACTIVE HALT mode, AWUFH has lower

power consumption because the main clock is not kept running, but there is no accurate

realtime clock available.

HALT

RUN

256 OR 4096 CYCLE

DELAY (AFTER RESET)

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

ACTIVE

(Active Halt enabled)

HALT INSTRUCTION

RESET

INTERRUPT 3)

CPU

OSCILLATOR

PERIPHERALS 2)

I[1:0] BITS

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

OFF

XX 4)

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

XX 4)

256 OR 4096 CPU CLOCK

CYCLE DELAY

(MCCSR.OIE=1)

(AWUCSR.AWUEN=0)

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