ST72361AR4-Auto datasheet(98/279 Pages) STMICROELECTRONICS

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PWM auto-reload timer (ART)

ST72361xx-Auto

98/279

Doc ID 12468 Rev 3

Bit 0 = OVF Overflow Flag

This bit is set by hardware and cleared by software reading the ARTCSR register. It

indicates the transition of the counter from FFh to the ARTARR value.

0: New transition not yet reached

1: Transition reached

Counter Access Register (ARTCAR)

Read/Write

Reset value: 0000 0000 (00h)

Bit 7:0 = CA[7:0] Counter Access Data

These bits can be set and cleared either by hardware or by software. The ARTCAR register

is used to read or write the auto-reload counter “on the fly” (while it is counting).

Auto-Reload Register (ARTARR)

Read/Write

Reset value: 0000 0000 (00h)

Bit 7:0 = AR[7:0] Counter Auto-Reload Data

These bits are set and cleared by software. They are used to hold the auto-reload value

which is automatically loaded in the counter when an overflow occurs. At the same time, the

PWM output levels are changed according to the corresponding OPx bit in the PWMCR

This register has two PWM management functions:

●

Adjusting the PWM frequency

●

Setting the PWM duty cycle resolution

CA7

CA6

CA5

CA4

CA3

CA2

CA1

CA0

AR7

AR6

AR5

AR4

AR3

AR2

AR1

AR0

Table 44.

PWM frequency vs resolution

ARTARR value

Resolution

fPWM

Min

Max

8-bit

~0.244 kHz

31.25 kHz

[0..127]

> 7-bit

~0.244 kHz

62.5 kHz

[128..191]

> 6-bit

~0.488 kHz

125 kHz

[192..223]

> 5-bit

~0.977 kHz

250 kHz

[224..239]

> 4-bit

~1.953 kHz

500 kHz

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