ST72361AR4-Auto datasheet(272/279 Pages) STMICROELECTRONICS

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Important notes

ST72361xx-Auto

272/279

Doc ID 12468 Rev 3

PUSH CC

.ext1_rt; entry to interrupt routine

LD A, #$00

LD sema, A

IRET

23.1.4

Unexpected reset fetch

If an interrupt request occurs while a "POP CC" instruction is executed, the interrupt

controller does not recognize the source of the interrupt and, by default, passes the RESET

vector address to the CPU.

Workaround

To solve this issue, a "POP CC" instruction must always be preceded by a "SIM" instruction.

23.1.5

Header time-out does not prevent wake-up from mute mode

Normally, when LINSCI is configured in LIN slave mode, if a header time-out occurs during a

LIN header reception (that is, header length > 57 bits), the LIN Header Error bit (LHE) is set,

an interrupt occurs to inform the application but the LINSCI should stay in mute mode,

waiting for the next header reception.

Problem description

The LINSCI sampling period is Tbit / 16. If a LIN Header time-out occurs between the 9th

and the 15th sample of the Identifier Field Stop Bit (refer to Figure 155), the LINSCI wakes

up from mute mode. Nevertheless, LHE is set and LIN Header Detection Flag (LHDF) is

kept cleared.

In addition, if LHE is reset by software before this 15th sample (by accessing the SCISR

generate another LINSCI interrupt (due to the RDRF flag setting).

Impact on application

Software may execute the interrupt routine twice after header reception.

Moreover, in reception mode, as the receiver is no longer in mute mode, an interrupt will be

generated on each data byte reception.

Workaround

The problem can be detected in the LINSCI interrupt routine. In case of timeout error (LHE

is set and LHLR is loaded with 00h), the software can check the RWU bit in the SCICR2

shown in bold characters.

ST72361AR4-Auto Datasheet(PDF) 272 Page - STMicroelectronics