STM32F328C8 datasheet(14/109 Pages) STMICROELECTRONICS

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Functional overview

STM32F328C8

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DocID026351 Rev 3

pin must be held low when VDDA is applied. Then, when VDD is stable, the reset state can

be exited by:

•

either putting the NPOR pin in high impedance. NPOR pin has an internal pull up

•

or forcing the pin to high level by connecting it to VDDA.

3.4.3

Low-power modes

The STM32F328C8 supports three low-power modes to achieve the best compromise

between low power consumption, short startup time and available wakeup sources:

•

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

•

Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC

and the HSE crystal oscillators are disabled. The voltage regulator can also be put

either in normal or in low-power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line

source can be one of the 16 external lines, the PVD output, the RTC alarm, COMPx,

I2C or USARTx.

Note:

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

mode.

3.5

Interconnect matrix

Several peripherals have direct connections between them. This allows autonomous

communication between peripherals, saving CPU resources thus power supply

consumption. In addition, these hardware connections allow fast and predictable latency.

Table 3. STM32F328C8 Peripheral interconnect matrix

Interconnect source

Interconnect

destination

Interconnect action

TIMx

Timers synchronization or chaining

ADCx

DACx

Conversion triggers

DMA

Memory to memory transfer trigger

COMPx

Comparator output blanking

COMPx

TIMx

Timer input: ocrefclear input, input capture

ADCx

TIM1

Timer triggered by analog watchdog

GPIO

RTCCLK

HSE/32

MC0

TIM16

Clock source used as input channel for HSI and

LSI calibration

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