STM32F383VC datasheet(84/125 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F383xx

84/125

DocID023367 Rev 2

In the user application, the number of I/O pins which can drive current must be limited to

respect the absolute maximum rating specified in Section 6.2:

•

The sum of the currents sourced by all the I/Os on all VDD_x and VDDSDx, plus the

maximum Run consumption of the MCU sourced on VDD cannot exceed the absolute

maximum rating ΣIVDD (see Table 20).

•

The sum of the currents sunk by all the I/Os on all VSS_x and VSSSD, plus the

maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute

maximum rating ΣIVSS (see Table 20).

Output voltage levels

Unless otherwise specified, the parameters given in Table 50 are derived from tests

performed under ambient temperature and VDD supply voltage conditions summarized in

Table 22. All I/Os are CMOS and TTL compliant (FT, TTa or TC unless otherwise specified).

Note:

I/O pins are powered from VDD voltage except pins which can be used as SDADC inputs:

- The PB10 and PE7 to PE15 I/O pins are powered from VDDSD12.

- PB14 to PB15 and PD8 to PD15 I/O pins are powered from VDDSD3. All I/O pin ground is

internally connected to VSS.

VDD mentioned in the Table 50 represents power voltage for a given I/O pin (VDD or

VDDSD12 or VDDSD3).

Table 50. Output voltage characteristics (1)

1. VDDSD12 is the external power supply for the PB10, and PE7 to PE15 I/O pins (the I/O pin ground is

internally connected to VSS). VDDSD3 is the external power supply for PB14 to PB15 and PD8 to PD15

I/O pins (the I/O pin ground is internally connected to VSS). For those pins all VDD supply references in this

table are related to their given VDDSDx power supply.

Symbol

Parameter

Conditions

Min

Max

Unit

VOL(2)

2. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 20

and the sum of IIO (I/O ports and control pins) must not exceed IVSS(Σ).

Output low level voltage for an I/O pin

IIO = +4 mA

1.65 V < VDD < 1.95 V

-0.4

VOH(3)

3. The IIO current sourced by the device must always respect the absolute maximum rating specified in

Table 20 and the sum of IIO (I/O ports and control pins) must not exceed IVDD(Σ).

Output high level voltage for an I/O

IIO = +4 mA

1.65 V < VDD < 1.95 V

VDD–0.4

VOL(2)(4)

Output low level voltage for an I/O pin

IIO = +8 mA

2.7 V < VDDSDx < 3.6 V

-0.4

VOH(3)(4)

Output high level voltage for an I/O

pin powered by VDDSDx(1)

VDDSDx

–0.4

VOL(2)(4)

4. Data based on design simulation.

Output low level voltage for an I/O pin

IIO = +20 mA

2.7 V < VDDSDx < 3.6 V

-1.3

VOH(3)(4)

Output high level voltage for an I/O

pin powered by VDDSDx(1)

VDDSDx

–1.3

VOLFM+(2)

Output low level voltage for a FTf I/O

pins in FM+ mode

IIO = +10 mA

1.65 V < VDD < 1.95 V

-0.4

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