AS4C8M32S datasheet(13/55 Pages) ALSC

13 / 55 page

AS4C8M32S

Alliance Memory Confidential

Rev. 2.0 May /2014

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CLK

ADDRESS

COMMAND

tRP

DQM

tWR

WRITE

Precharge

NOP

Activate

NOP

BANK

COL n

BANK(S)

ROW

DIN

N+1

NOP

Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.

Figure 13. Write to Precharge

Write and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "H",

A0-A8 = Column Address)

The Write and AutoPrecharge command performs the precharge operation automatically after the

write operation. Once this command is given, any subsequent command can not occur within a time

delay of {(burst length -1) + tWR + tRP (min.)}. At full-page burst, only the write operation is performed

in this command and the auto precharge function is ignored.

CLK

COMMAND

tDAL

tDAL=tWR+tRP

Begin AutoPrecharge

Bank can be reactivated at

completion of tDAL

Bank A

Activate

NOP

Auto Precharge

Write A

DIN A0

DIN A1

NOP

Bank A

Activate

Figure 14. Burst Write with Auto-Precharge (Burst Length = 2)

Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A11 = Register Data)

The mode register stores the data for controlling the various operating modes of SDRAM. The

Mode Register Set command programs the values of CAS latency, Addressing Mode and Burst

Length in the Mode register to make SDRAM useful for a variety of different applications. The default

values of the Mode Register after power-up are undefined; therefore this command must be issued at

the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to the

mode register. Two clock cycles are required to complete the write in the mode register (refer to the

following figure). The contents of the mode register can be changed using the same command and

the clock cycle requirements during operation as long as all banks are in the idle state.

AS4C8M32S Datasheet(PDF) 13 Page - Alliance Semiconductor Corporation

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