AS4C8M32S datasheet(21/55 Pages) ALSC

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AS4C8M32S

Alliance Memory Confidential

Rev. 2.0 May /2014

Table 14. Electrical Characteristics and Recommended A.C. Operating Conditions

(VDD = 3.3V±0.3V, TA = -40~85°C) (Note: 5, 6, 7, 8)

Symbol

A.C. Parameter

-6

-75

Unit Note

Min.

Max.

Min.

Max.

tRC

Row cycle time

(same bank)

67.5

tRCD

RAS# to CAS# delay

(same bank)

22.5

tRP

Precharge to refresh/row activate command

(same bank)

22.5

tRRD

Row activate to row activate delay

(different banks)

tRAS

Row activate to precharge time

(same bank)

100k

tWR

Write recovery time

tCK

tCCD

CAS# to CAS# Delay time

tCK

Clock cycle time

CL* = 2

CL* = 3

7.5

tCH

Clock high time

2.5

tCL

Clock low time

2.5

tAC

Access time from CLK

(positive edge)

CL* = 2

CL* = 3

5.4

tOH

Data output hold time

tLZ

Data output low impedance

tHZ

Data output high impedance

5.4

tIS

Data/Address/Control Input set-up time

tIH

Data/Address/Control Input hold time

tPDE

Power Down Exit set-up time

tIS+ tCK

tREFI

Average Refresh Interval Time

15.6

s

tDAL

Last data in to active latency

tCK

tXSR

Exit Self Refresh to Read Command time

tIS+ tRC

CL is CAS Latency.

Note:

1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to

the device.

2. All voltages are referenced to VSS. VIH (Max) = 4.6V for pulse width ≤ 3ns. VIL (Min) = -1.0V for pulse

width ≤ 3ns.

3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the

minimum value of tCK and tRC. Input signals are changed one time during every 2 tCK.

4. These parameters depend on the output loading. Specified values are obtained with the output open.

5. Power-up sequence is described in Note 11.

6. A.C. Test Conditions

AS4C8M32S Datasheet(PDF) 21 Page - Alliance Semiconductor Corporation

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