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AS4C64M8D1 Datasheet(PDF) 13 Page - Alliance Semiconductor Corporation |
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AS4C64M8D1 Datasheet(HTML) 13 Page - Alliance Semiconductor Corporation |
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13 / 64 page  AS4C64M8D1 Confidential 12 Rev. 2.0 Oct. /2014 Table 16. Electrical Characteristics and Recommended A.C.Operating Condition (VDD = 2.5V ± 0.2V, TA = 0 ~ 70 C) Symbol Parameter -5 Unit Note Min. Max. tCK Clock cycle time CL = 2 7.5 12 ns CL = 2.5 6 12 ns CL = 3 5 12 ns tCH Clock high level width 0.45 0.55 tCK tCL Clock low level width 0.45 0.55 tCK tHP Clock half period tCLMIN or tCHMIN - ns 2 tHZ Data-out-high impedance time from CK, CK - 0.7 ns 3 tLZ Data-out-low impedance time from CK, CK -0.7 0.7 ns 3 tDQSCK DQS-out access time from CK, CK -0.6 0.6 ns tAC Output access time from CK, CK -0.7 0.7 ns tDQSQ DQS-DQ Skew - 0.4 ns tRPRE Read preamble 0.9 1.1 tCK tRPST Read postamble 0.4 0.6 tCK tDQSS CK to valid DQS-in 0.72 1.25 tCK tWPRES DQS-in setup time 0 - ns 4 tWPRE DQS Write preamble 0.25 - tCK tWPST DQS write postamble 0.4 0.6 tCK 5 tDQSH DQS in high level pulse width 0.35 - tCK tDQSL DQS in low level pulse width 0.35 - tCK tIS Address and Control input setup time 0.7 - ns 6 tIH Address and Control input hold time 0.7 - ns 6 tDS DQ & DM setup time to DQS 0.4 - ns tDH DQ & DM hold time to DQS 0.4 - ns tQH DQ/DQS output hold time from DQS tHP - tQHS - ns tRC Row cycle time 55 - ns tRFC Refresh row cycle time 70 - ns tRAS Row active time 40 70K ns tRCD Active to Read or Write delay 15 - ns tRP Row precharge time 15 - ns tRRD Row active to Row active delay 10 - ns tWR Write recovery time 15 - ns tWTR Internal Write to Read Command Delay 2 - tCK tMRD Mode register set cycle time 10 - ns tREFI Average Periodic Refresh interval - 7.8 s 7 tXSRD Self refresh exit to read command delay 200 - tCK tXSNR Self refresh exit to non-read command delay 75 - ns tDAL Auto Precharge write recovery + precharge time tWR+tRP - ns tDIPW DQ and DM input pulse width 1.75 - ns tIPW Control and Address input pulse width 2.2 - ns tQHS Data Hold Skew Factor - 0.5 ns tDSS DQS falling edge to CK setup time 0.2 - tCK tDSH DQS falling edge hold time from CK 0.2 - tCK |
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