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STR710FZ1 Datasheet(PDF) 77 Page - STMicroelectronics |
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STR710FZ1 Datasheet(HTML) 77 Page - STMicroelectronics |
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77 / 80 page ![]() STR71xFxx STR710RZ Known limitations Doc ID 10350 Rev 13 77/80 8 Known limitations Description If an IRQ or FIQ interrupt is pending and the Interrupt vector register (EIC_IVR) is not yet read, the HALT bit in the RCCU_SMR register can not be written. Therefore a software reset can not be generated. Workaround To generate a software reset when an IRQ or FIQ line is pending, either: ● reset the EIC peripheral by setting bit 14 in the APB2_SWRES register, or ● read the EIC_IVR register prior to generating a software reset. |
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