L9658 datasheet(50/64 Pages) STMICROELECTRONICS

50 / 64 page

Functional description

L9658

50/64

Doc ID 14219 Rev 3

Upon power up or after a reset, the device requires at least 1.5 Idle bit-time based on

52.33khz protocol speed or 28.65us before starting to decode the first message, bit-time

shall adapt to the period obtained based on the two sync bits there after.

4.14.3

Communication protocols

The L9658 supports two different communication protocols that are widely used by different

automotive manufactures. One is based on the protocol used by "A" satellite sensors and

the other is "B" protocol that supports variable length messages based on BOSH, PAS3 and

PAS4 protocols. Bits D11D12 in the CCR Register are used to configure the device in order

to use any of these protocols.

4.14.4

"A" protocol

The Delphi sensors satellites protocol supported by this device is shown below. The

message consists of 5 bits CRC cyclic redundancy check error, 12 bit of data and two sync

bits. This information could be sensor’s trace-ability data, or crash severity or velocity data.

The two most significant bits in the data field sent by the sensor can identify these data

types.

Figure 21.

"A" satellite protocol

The CRC error detection code is based on the polynomial x5 + x2+ 1. The L9658 processes

all incoming message through the CRC verification and report an error message via SPI in

case of a CRC mismatch. CRC is performed after a complete message is received, and in

case of CRC error, he device sets a fault code via SPI.

4.14.5

"B" variable length protocol

Figure 22.

"B" satellite protocol

The L9658 IC shall supports "B" satellite protocol, which is based on Bosch sensors

PAS3\PAS4 protocols (In Figure 22 bit order is opposite to PAS3/PAS4 protocol in which

LSB is sent first and MSB last) with added flexibility that the message length in the data field

can be programmed to accept any number of bits between 8 and 11. The protocol consists

of a parity bit, a data field (configurable between 8 to 11 bits) and two sync bits. The IC can

be enabled to use this protocol through the appropriate setting in the MCR register. Once

the protocol is enabled for a specific channel, the protocol speed is configured by setting the

appropriate bits in the CCR register for that particular channel. A parity check is performed

after a complete message is received, and in case of a parity error, the device sets a fault

code via SPI.

DATA

CRC

SYNC1

IDLE

MSB

LSB

SYNC2

IDLE2

IDLE1

DATA

SYNC1

IDLE

LSB

SYNC2

IDLE2

IDLE1

MSB

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