L9658 datasheet(51/64 Pages) STMICROELECTRONICS

51 / 64 page

L9658

Functional description

Doc ID 14219 Rev 3

51/64

4.14.6

FIFO buffer

The IC includes 4 internal FIFO buffers; one for each output channel, each one is 12 bits

and two levels deep. When D1 in the MCR register is set to 0 (default condition), MSG pin is

asserted and remain asserted as long as there is a message in any of the 4 internal FIFO

buffers.

The FIFO provides error flag via SPI in case of buffer data loss. When writing to a full FIFO

the old data is lost. For example if the FIFO content at the bottom of the stack is $0AA, an

incoming message of $090 will occupy the upper level of the FIFO stack, at this stage the

FIFO is full, but the Data lost flag is not set. When writing another message to the FIFO, for

example $066, the Data lost flag is set and the final FIFO content is $066 (top of stack) and

$090(bottom of stack). When a FIFO read operation is performed via SPI, The FIFO content

$090 is carried over by MISO and Data lost flag is unset. The Data lost flag is also unset

when the FIFO is flushed via SPI command.

4.14.7

Satellite continuity check

Each output has a short circuit protection by independent current limit. When a short circuit

occurs the output becomes current limited, a fault timer latch the output off and a fault

condition bit is reported via SPI.

That output returns to normal operation when it is re-enabled via SPI and the current limit

condition was removed, this fault condition does not interfere with the operation of any of the

other output channels

4.14.8

(IFx/Vx) hall effect support mode

Channels 3 and 4 of the L9658 can by used to provide an analog feed back current as a

1/100th ratio of the sense current in this mode internal FIFO and decoder are bypassed.

This will allow the IF3/V3 and IF4/V4 pins to be connected to a resistor to ground and

provide an analog voltage equivalent to the sense current to be read by an A/D port. These

two pins have an internal clamp as protection.

This mode of operation is accessed by the setting of D4 and D5 in the MCR register. When

D4 and D5 are set to 1, pins IF3/V3 and IF4V4 is configured as analog current output with

1/100th ratio of the sense current. This feature is available for Channels 3 and 4.

4.14.9

(IFx/Vx) raw data out mode

When D4 and D5 in the MCR register are set to 0 the IF3/V3 and IF4/V4 pins are configured

as discrete output pins that provide logic level output voltage of the sensed current based on

the internal current threshold set by the user through the CCR Register, which when used in

conjunction with satellite sensors connected to channels 3 and 4 it can provide raw data out

of the satellite message bypassing the internal decoder.

The output voltage has a reversed polarity to the satellite current such that when the current

drawn by the satellite is below the current detection threshold, the IFx/Vx signal level

transitions into a high state, on the other hand if the current drawn by the satellite exceed the

current detection threshold, IFx/Vx signal transitions into a low state. Bits D6 and D7 in the

MCR register is used to disable this output if it is not used.

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